00001 /* Copyright 2008, 2009 Fred Cooke 00002 00003 This file is part of the FreeEMS project. 00004 00005 FreeEMS software is free software: you can redistribute it and/or modify 00006 it under the terms of the GNU General Public License as published by 00007 the Free Software Foundation, either version 3 of the License, or 00008 (at your option) any later version. 00009 00010 FreeEMS software is distributed in the hope that it will be useful, 00011 but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 GNU General Public License for more details. 00014 00015 You should have received a copy of the GNU General Public License 00016 along with any FreeEMS software. If not, see http://www.gnu.org/licenses/ 00017 00018 We ask that if you make any changes to this file you email them upstream to 00019 us at admin(at)diyefi(dot)org or, even better, fork the code on github.com! 00020 00021 Thank you for choosing FreeEMS to run your engine! */ 00022 00023 00040 /* see if we've seen this, if not, mark seen and process */ 00041 #ifndef FILE_9S12XDP512_H_SEEN 00042 #define FILE_9S12XDP512_H_SEEN 00043 00044 00045 /* shortcuts to speed formatting */ 00046 /* www.atmel.com/dyn/resources/prod_documents/avr_3_04.pdf First page, second column */ 00047 /* http://www.ee.nmt.edu/~rison/ee308_spr06/homepage.html */ 00048 /* extra parentheses for clarity and guarantee of precedence */ 00049 00050 /* Dereferenced Volatile Unsigned Char Pointer */ 00051 #define DVUCP(address) (*((volatile unsigned char*)(address))) 00052 /* Dereferenced Volatile Unsigned Short Pointer */ 00053 #define DVUSP(address) (*((volatile unsigned short*)(address))) 00054 00055 /* Address Volatile Unsigned Char Pointer */ 00056 #define AVUCP(address) ((volatile unsigned char*)(address)) 00057 /* Address Volatile Unsigned Short Pointer */ 00058 #define AVUSP(address) ((volatile unsigned short*)(address)) 00059 00060 00061 00062 /* Port Integration Module - Reordered within sections for clarity */ 00063 /* PIM information from 5 tables the last of which is spread over three pages */ 00064 00065 /* Plain ports output switch, input state registers */ 00066 #define PORTS_BA DVUSP(0x0001) /* Both A and B combined as a 16 bit register for ignition access */ 00067 #define PORTA DVUCP(0x0000) 00068 #define PORTB DVUCP(0x0001) 00069 #define PORTE DVUCP(0x0008) 00070 #define PORTK DVUCP(0x0032) 00071 /* #define PORTC DVUCP(0x0004) these pins are not bonded on the 112 pin package */ 00072 /* #define PORTD DVUCP(0x0005) these pins are not bonded on the 112 pin package */ 00073 00074 00075 /* Plain ports Data Direction Registers */ 00076 #define DDRA DVUCP(0x0002) 00077 #define DDRB DVUCP(0x0003) 00078 #define DDRE DVUCP(0x0009) 00079 #define DDRK DVUCP(0x0033) 00080 00081 00082 #define DDRC DVUCP(0x0006) /* these pins are not bonded on the 112 pin package but need switching to output */ 00083 #define DDRD DVUCP(0x0007) /* these pins are not bonded on the 112 pin package but need switching to output */ 00084 00085 00086 /* 0b1//1//00 */ 00087 /* --K//E//BA */ 00088 /* TODO NOTE: the sixth bit controls pull up on BKGD and VREGEN pins set this to ???? */ 00089 /* NOTE: pull up on port E is for 0-4 and 7, ports 5 and 6 are pulled down during reset and never pulled up. */ 00090 #define PUCR DVUCP(0x000C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */ 00091 00092 00093 /* 0b1//0//00 */ 00094 /* --K//E//BA */ 00095 /* NOTE: reduced drive affects all pins of all ports listed above. */ 00096 #define RDRIV DVUCP(0x000D) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */ 00097 00098 00099 #define ECLKCTL DVUCP(0x001C) /* Comes up 0b_1100_0000 = both pins off in normal single chip mode */ 00100 #define IRQCR DVUCP(0x001E) /* 0 in bit 7 makes it ultra sensitive, 1 makes it falling edge sensitive. 0 in bit 6 turns interrupts off, 1 in bit 6 turns them on. */ 00101 00102 00103 /* Port T registers */ 00104 #define PTT DVUCP(0x0240) /* GPIO output register, can not be read from reliably, use PTIT instead */ 00105 #define PORTT DVUCP(0x0240) /* Duplicate definition for consistency */ 00106 #define PTIT DVUCP(0x0241) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */ 00107 #define DDRT DVUCP(0x0242) /* TODO configure all IO as outputs until we need it */ 00108 #define RDRT DVUCP(0x0243) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */ 00109 #define PERT DVUCP(0x0244) /* pull up/down enable when used as an input, 0 = no pull up, 1 = pull up on */ 00110 #define PPST DVUCP(0x0245) /* 0 = pull up, 1 = pull down */ 00111 00112 00113 /* Port S registers */ 00114 #define PTS DVUCP(0x0248) 00115 #define PORTS DVUCP(0x0248) /* Duplicate definition for consistency */ 00116 #define PTIS DVUCP(0x0249) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */ 00117 #define DDRS DVUCP(0x024A) /* TODO configure all IO as outputs until we need it */ 00118 #define RDRS DVUCP(0x024B) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */ 00119 #define PERS DVUCP(0x024C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */ 00120 #define PPSS DVUCP(0x024D) /* 0 = pull up, 1 = pull down */ 00121 #define WOMS DVUCP(0x024E) /* wired OR mode TODO find out what this actually means in real terms. */ 00122 00123 00124 /* Port M registers */ 00125 #define PTM DVUCP(0x0250) 00126 #define PORTM DVUCP(0x0250) /* Duplicate definition for consistency */ 00127 #define PTIM DVUCP(0x0251) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */ 00128 #define DDRM DVUCP(0x0252) /* TODO configure all IO as outputs until we need it */ 00129 #define RDRM DVUCP(0x0253) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */ 00130 #define PERM DVUCP(0x0254) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */ 00131 #define PPSM DVUCP(0x0255) /* 0 = pull up, 1 = pull down */ 00132 #define WOMM DVUCP(0x0256) /* wired OR mode TODO find out what this actually means in real terms. */ 00133 00134 00135 /* this should be set to the following bit mask xx????00 */ 00136 #define MODRR DVUCP(0x0257) 00137 00138 00139 /* Port P registers */ 00140 #define PTP DVUCP(0x0258) 00141 #define PORTP DVUCP(0x0258) /* Duplicate definition for consistency */ 00142 #define PTIP DVUCP(0x0259) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */ 00143 #define DDRP DVUCP(0x025A) /* TODO configure all IO as outputs until we need it */ 00144 #define RDRP DVUCP(0x025B) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */ 00145 #define PERP DVUCP(0x025C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */ 00146 #define PPSP DVUCP(0x025D) /* 0 = pull up, 1 = pull down AND when IE pull down means I on rising edge and pull up means I on falling edge */ 00147 #define PIEP DVUCP(0x025E) /* interrupt enable, turns on interrupts */ 00148 #define PIFP DVUCP(0x025F) /* interrupt flag, write a 1 to clear it */ 00149 00150 00151 /* Port H registers */ 00152 #define PTH DVUCP(0x0260) 00153 #define PORTH DVUCP(0x0260) /* Duplicate definition for consistency */ 00154 #define PTIH DVUCP(0x0261) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */ 00155 #define DDRH DVUCP(0x0262) /* TODO configure all IO as outputs until we need it */ 00156 #define RDRH DVUCP(0x0263) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */ 00157 #define PERH DVUCP(0x0264) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */ 00158 #define PPSH DVUCP(0x0265) /* 0 = pull up, 1 = pull down AND when IE pull down means I on rising edge and pull up means I on falling edge */ 00159 #define PIEH DVUCP(0x0266) /* interrupt enable, turns on interrupts */ 00160 #define PIFH DVUCP(0x0267) /* interrupt flag, write a 1 to clear it */ 00161 00162 00163 /* Port J registers */ 00164 #define PTJ DVUCP(0x0268) 00165 #define PORTJ DVUCP(0x0268) /* Duplicate definition for consistency */ 00166 #define PTIJ DVUCP(0x0269) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */ 00167 #define DDRJ DVUCP(0x026A) /* TODO configure all IO as outputs until we need it */ 00168 #define RDRJ DVUCP(0x026B) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */ 00169 #define PERJ DVUCP(0x026C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */ 00170 #define PPSJ DVUCP(0x026D) /* 0 = pull up, 1 = pull down AND when IE pull down means I on rising edge and pull up means I on falling edge */ 00171 #define PIEJ DVUCP(0x026E) /* interrupt enable, turns on interrupts */ 00172 #define PIFJ DVUCP(0x026F) /* interrupt flag, write a 1 to clear it */ 00173 00174 00175 /* #define ATD0PT1 DVUCP(0x0271) we don't want to use valuable ATD pins as normal IO, but if we did, r/w here */ 00176 /* #define ATD0DDR1 DVUCP(0x0273) for use as an input, ATD0DIEN has to be set to 1. for use as an output? */ 00177 /* #define ATD0RDR1 DVUCP(0x0275) reduced drive register when used as output, 0 = full drive, 1 = reduced drive */ 00178 #define ATD0PER1 DVUCP(0x0277) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */ 00179 00180 /* #define ATD1PT1 DVUCP(0x0279) we don't want to use valuable ATD pins as normal IO, but if we did, r/w here */ 00181 /* #define ATD1DDR1 DVUCP(0x027B) for use as an input, ATD1DIEN1 has to be set to 1. for use as an output? */ 00182 /* #define ATD1RDR1 DVUCP(0x027D) reduced drive register when used as output, 0 = full drive, 1 = reduced drive */ 00183 /* #define ATD1PER1 DVUCP(0x027F) pull up enable when used as an input, 0 = no pull up, 1 = pull up on */ 00184 00185 /* Not available on 112 pin version */ 00186 /* #define ATD1DDR0 DVUCP(0x027A) */ 00187 /* 0x0278 #define ATD1PT0 DVUCP() */ 00188 /* 0x027C #define ATD1RDR0 DVUCP() */ 00189 /* 0x027E #define ATD1PER0 DVUCP() */ 00190 00191 00192 /* Memory Mapping Control registers TODO configure these to suit our application. */ 00193 /* MMC 1/4 */ 00194 //0x000B MODE DVUCP() 00195 //0x000A MMCCTL0 DVUCP() 00196 //0x0013 MMCCTL1 DVUCP() 00197 00198 00199 /* Page control registers */ 00200 #define RPAGE DVUCP(0x0016) /* Used to page table data in and out of visible memory. */ 00201 //0x0017 EPAGE DVUCP() /* /* TODO similar to above if we need another 2k of eeprom. what are advantages/disadvantages of eeprom over flash?? */ 00202 #define PPAGE DVUCP(0x0030) /* TODO look at the best way to use the flash space in a complete system with a lot of code and data. used by compiler and maybe us to switch flash pages for loading/unloading data. */ 00203 //0x0010 GPAGE DVUCP() /* /* Global page register for global instruction addressing. I doubt we will use this. */ 00204 //0x0011 DIRECT DVUCP() /* /* Direct addressing mode control register. I doubt we will use this. */ 00205 00206 00208 //0x011C RAMWPC /* RAM Write Protection register, the pdf document appears to be incorrect for this, best not to touch it. */ 00209 //0x011D RAMXGU /* XGATE Upper region limit, this defines how much RAM we give the xgate to work with. */ 00210 //0x011E RAMSHL /* Shared memory lower boundary register, this defines the lower limit of the overlap between XGATE RAM and CPU RAM */ 00211 //0x011F RAMSHU /* Shared memory upper boundary register, this defines the upper limit of the overlap between XGATE RAM and CPU RAM */ 00212 00213 00215 //0x000E EBICTL0 DVUCP() /* 00216 //0x000F EBICTL1 DVUCP() /* 00217 00218 00220 //0x001A PARTIDH DVUCP() /* 00221 //0x001B PARTIDL DVUCP() /* 00222 00223 00224 /* Clock and Reset Generator */ 00225 #define SYNR DVUCP(0x0034) /* Multiplier of result of division by REFDV below, output is new PLL/Bus freqency. */ 00226 #define REFDV DVUCP(0x0035) /* Divisor of external clock frequency pre being multiplied by SYNR above. */ 00227 //0x0036 CTFLG DVUCP() /* 00228 #define CRGFLG DVUCP(0x0037) /* Clock and Reset Generator flags, we use this to determine when the PLL is stable and ready to use. Also to reset the RTI flag. */ 00229 #define CRGINT DVUCP(0x0038) /* Bit 7 is RTIE RTI enable bit. */ 00230 #define CLKSEL DVUCP(0x0039) /* Clock select register, choose PLL or external clock with this. */ 00231 #define PLLCTL DVUCP(0x003A) /* PLL frequency generator control register, used for setting the bus frequency. */ 00232 #define RTICTL DVUCP(0x003B) /* Divider select register */ 00233 #define COPCTL DVUCP(0x003C) /* COP watch dog control register */ 00234 //0x003D FORBYP DVUCP() /* 00235 #define ARMCOP DVUCP(0x003F) /* Computer operating properly timer, we won't be using this at least until we have profiled the running application. it will just cause headaches otherwise. */ 00236 00237 00238 /* Enhanced Capture Timer */ 00239 /* see reference document from Huang course overview/notes : http://www.ee.nmt.edu/~rison/ee308_spr06/lectures.html */ 00240 /* see this link for a discussion of the old 68hc12 timer http://www.seattlerobotics.org/encoder/nov97/68hc12.html */ 00241 00242 #define TCNT DVUSP(0x0044) /* Timer counter 16 bit (0x0044 TCNT (hi), 0x0045 TCNT (lo)) */ 00243 00244 /* Behavioural control registers (dual purpose) */ 00245 #define TIOS DVUCP(0x0040) /* Selects input capture or output compare mode for each timer pin */ 00246 #define TIE DVUCP(0x004C) /* Timer channel interrupt enable register */ 00247 #define TSCR1 DVUCP(0x0046) /* Timer System Control Register 1 */ 00248 #define TSCR2 DVUCP(0x004D) /* Timer System Control Register 2 */ 00249 #define TFLG DVUCP(0x004E) /* Timer channel flags */ 00250 #define TFLGOF DVUCP(0x004F) /* Timer over flow flag */ 00251 #define PTPSR DVUCP(0x006E) /* Precision prescaler for the main timer */ 00252 00253 /* Output compare control registers */ 00254 #define TTOV DVUCP(0x0047) /* Timer Toggle on Overflow output compare control */ 00255 #define CFORC DVUCP(0x0041) /* Output compare force, write a 1 to make the programmed action occur now */ 00256 #define OC7M DVUCP(0x0042) /* Channel 7 output compare other pins control mask */ 00257 #define OC7D DVUCP(0x0043) /* Channel 7 output compare other pins states */ 00258 00259 /* Timer output compare action control registers 00260 * OMx OLx Action 00261 * 0 0 Timer disconnected from output pin logic 00262 * 0 1 Toggle OCx output line 00263 * 1 0 Clear OCx output line to zero 00264 * 1 1 Set OCx output line to one */ 00265 #define TCTL1 DVUCP(0x0048) /* (M,L) 77,66,55,44 */ 00266 #define TCTL2 DVUCP(0x0049) /* (M,L) 33,22,11,00 */ 00267 #define TCTL1_ADDR AVUCP(0x0048) /* (M,L) 77,66,55,44 */ 00268 #define TCTL2_ADDR AVUCP(0x0049) /* (M,L) 33,22,11,00 */ 00269 00270 00271 /* Input capture control registers */ 00272 #define DLYCT DVUCP(0x0069) /* Delay counter control register (minimum tooth width) */ 00273 #define ICSYS DVUCP(0x006B) /* Input capture behaviour control register */ 00274 #define ICOVW DVUCP(0x006A) /* Input capture overwrite allow */ 00275 00276 /* Timer input capture edge detection control registers 00277 * EDGxB EDGxA Configuration 00278 * 0 0 Capture disabled 00279 * 0 1 Capture on rising edges only 00280 * 1 0 Capture on falling edges only 00281 * 1 1 Capture on any edge (rising or falling) */ 00282 #define TCTL3 DVUCP(0x004A) /* (B,A) 77,66,55,44 */ 00283 #define TCTL4 DVUCP(0x004B) /* (B,A) 33,22,11,00 */ 00284 00285 /* Input capture holding registers for 0 - 3 */ 00286 #define TC0H DVUSP(0x0078) /* 16 bit (0x0078 TC0H (hi), 0x0079 TC0H (lo)) */ 00287 #define TC1H DVUSP(0x007A) /* 16 bit (0x007A TC1H (hi), 0x007B TC1H (lo)) */ 00288 #define TC2H DVUSP(0x007C) /* 16 bit (0x007C TC2H (hi), 0x007D TC2H (lo)) */ 00289 #define TC3H DVUSP(0x007E) /* 16 bit (0x007E TC3H (hi), 0x007F TC3H (lo)) */ 00290 00291 /* Time value comparison/storage registers for each timer channel */ 00292 #define TC0 DVUSP(0x0050) /* 16 bit (0x0050 TC0 (hi), 0x0051 TC0 (lo)) */ 00293 #define TC1 DVUSP(0x0052) /* 16 bit (0x0052 TC1 (hi), 0x0053 TC1 (lo)) */ 00294 #define TC2 DVUSP(0x0054) /* 16 bit (0x0054 TC2 (hi), 0x0055 TC2 (lo)) */ 00295 #define TC3 DVUSP(0x0056) /* 16 bit (0x0056 TC3 (hi), 0x0057 TC3 (lo)) */ 00296 #define TC4 DVUSP(0x0058) /* 16 bit (0x0058 TC4 (hi), 0x0059 TC4 (lo)) */ 00297 #define TC5 DVUSP(0x005A) /* 16 bit (0x005A TC5 (hi), 0x005B TC5 (lo)) */ 00298 #define TC6 DVUSP(0x005C) /* 16 bit (0x005C TC6 (hi), 0x005D TC6 (lo)) */ 00299 #define TC7 DVUSP(0x005E) /* 16 bit (0x005E TC7 (hi), 0x005F TC7 (lo)) */ 00300 00301 #define TC2_ADDR AVUSP(0x0054) /* 16 bit (0x0054 TC2 (hi), 0x0055 TC2 (lo)) */ 00302 #define TC3_ADDR AVUSP(0x0056) /* 16 bit (0x0056 TC3 (hi), 0x0057 TC3 (lo)) */ 00303 #define TC4_ADDR AVUSP(0x0058) /* 16 bit (0x0058 TC4 (hi), 0x0059 TC4 (lo)) */ 00304 #define TC5_ADDR AVUSP(0x005A) /* 16 bit (0x005A TC5 (hi), 0x005B TC5 (lo)) */ 00305 #define TC6_ADDR AVUSP(0x005C) /* 16 bit (0x005C TC6 (hi), 0x005D TC6 (lo)) */ 00306 #define TC7_ADDR AVUSP(0x005E) /* 16 bit (0x005E TC7 (hi), 0x005F TC7 (lo)) */ 00307 00308 00309 00310 /* Pulse accumulator control registers */ 00311 #define ICPAR DVUCP(0x0068) 00312 /* (PACTL) 7 6 5 4 3 2 1 0 00313 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI */ 00314 #define PACTL DVUCP(0x0060) 00315 #define PAFLG DVUCP(0x0061) 00316 #define PBCTL DVUCP(0x0070) 00317 #define PBFLG DVUCP(0x0071) 00318 /* Pulse accumulator count registers dual access, 8 or 16 bit */ 00319 #define PACNUS2 DVUSP(0x0062) /* 16 bit (0x0062 PACN3, 0x0063 PACN2) */ 00320 #define PACNUS0 DVUSP(0x0064) /* 16 bit (0x0064 PACN1, 0x0065 PACN0) */ 00321 #define PACN3 DVUCP(0x0062) /* high */ 00322 #define PACN2 DVUCP(0x0063) /* low */ 00323 #define PACN1 DVUCP(0x0064) /* high */ 00324 #define PACN0 DVUCP(0x0065) /* low */ 00325 /* Pulse accumulator holding registers dual access, 8 or 16 bit */ 00326 #define PACHUS2 DVUSP(0x0072) /* 16 bit (0x0072 PACH3, 0x0073 PACH2) */ 00327 #define PACHUS0 DVUSP(0x0074) /* 16 bit (0x0074 PACH1, 0x0075 PACH0) */ 00328 #define PA3H DVUCP(0x0072) /* high */ 00329 #define PA2H DVUCP(0x0073) /* low */ 00330 #define PA1H DVUCP(0x0074) /* high */ 00331 #define PA0H DVUCP(0x0075) /* low */ 00332 00333 00334 /* Modulus down counter control registers */ 00335 #define MCCTL DVUCP(0x0066) /* Modulus control register */ 00336 #define MCFLG DVUCP(0x0067) /* Modulus flag (high bit) and input edge indicators (low 4 bits) */ 00337 #define MCCNT DVUSP(0x0076) /* 16 bit (0x0076 MCCNT (hi), 0x0077 MCCNT (lo)) */ 00338 #define PTMCPSR DVUCP(0x006F) /* Precision prescaler for the modulus down counter */ 00339 00340 00341 /* Analog To Digital converter 1 */ 00342 /* TODO Configure these and disable the non functional 16 - 23 144 pin section! */ 00343 #define ATD1CTL0 DVUCP(0x0080) /* 0 - 3 define which ADC channel to wrap on when doing multiple channels */ 00344 #define ATD1CTL1 DVUCP(0x0081) /* External trigger select when enabled in other control register */ 00345 #define ATD1CTL2 DVUCP(0x0082) /* bit 7 turns the ADC block on. */ 00346 #define ATD1CTL3 DVUCP(0x0083) /* bit 6 means conversion length is 8, bit 2 controls how the registers are used, bits 0 - 1 define freeze mode behaviour */ 00347 #define ATD1CTL4 DVUCP(0x0084) /* bit 7 should be zero meaning 10bit ADC, bits 6,5 are the sample period, and 4,3,2,1,0 are the sample frequency clock scaler */ 00348 #define ATD1CTL5 DVUCP(0x0085) /* bit 7 sets right justify, bit 5 sets scan mode, bit 4 sets multiplex mode */ 00349 //0x0086 ATD1STAT0 DVUCP() /* 00350 //0x0088 ATD1TEST0 DVUCP() /* 00351 //0x0089 ATD1TEST1 DVUCP() /* 00352 //0x008A ATD1STAT2 DVUCP() /* 00353 //0x008B ATD1STAT1 DVUCP() /* 00354 #define ATD1DIEN0 DVUCP(0x008C) /* Digital input enable - these pins are not bonded on the 112 pin package */ 00355 #define ATD1DIEN1 DVUCP(0x008D) /* Digital input enable */ 00356 //0x008E ATD1PTAD0 DVUCP() /* digital use only */ 00357 //0x008F ATD1PTAD1 DVUCP() /* digital use only */ 00358 // one short for each hi lo par based on hi address. label with WORD for consistency 00359 #define ATD1_BASE 0x0090 00360 #define ATD1DR0 DVUSP(ATD1_BASE + 0x0) /* 16 bit (0x0090 ATD1DR0H, 0x0091 ATD1DR0L) */ /* SpareADC (NC) */ 00361 #define ATD1DR1 DVUSP(ATD1_BASE + 0x2) /* 16 bit (0x0092 ATD1DR1H, 0x0093 ATD1DR1L) */ /* SpareADC (NC) */ 00362 #define ATD1DR2 DVUSP(ATD1_BASE + 0x4) /* 16 bit (0x0094 ATD1DR2H, 0x0095 ATD1DR2L) */ /* SpareADC (NC) */ 00363 #define ATD1DR3 DVUSP(ATD1_BASE + 0x6) /* 16 bit (0x0096 ATD1DR3H, 0x0097 ATD1DR3L) */ /* SpareADC (NC) */ 00364 #define ATD1DR4 DVUSP(ATD1_BASE + 0x8) /* 16 bit (0x0098 ATD1DR4H, 0x0099 ATD1DR4L) */ /* SpareADC (NC) */ 00365 #define ATD1DR5 DVUSP(ATD1_BASE + 0xA) /* 16 bit (0x009A ATD1DR5H, 0x009B ATD1DR5L) */ /* SpareADC (NC) */ 00366 #define ATD1DR6 DVUSP(ATD1_BASE + 0xC) /* 16 bit (0x009C ATD1DR6H, 0x009D ATD1DR6L) */ /* SpareADC (NC) */ 00367 #define ATD1DR7 DVUSP(ATD1_BASE + 0xE) /* 16 bit (0x009E ATD1DR7H, 0x009F ATD1DR7L) */ /* SpareADC (NC) */ 00368 00369 00370 /* NOT bonded on the 112 pin package!! Left here in case of 144 pin FreeEMS later on. */ 00371 //0x00A0 ATD1DR8H 00372 //0x00A1 ATD1DR8L 00373 //0x00A2 ATD1DR9H 00374 //0x00A3 ATD1DR9L 00375 //0x00A4 ATD1DR10H 00376 //0x00A5 ATD1DR10L 00377 //0x00A6 ATD1DR11H 00378 //0x00A7 ATD1DR11L 00379 //0x00A8 ATD1DR12H 00380 //0x00A9 ATD1DR12L 00381 //0x00AA ATD1DR13H 00382 //0x00AB ATD1DR13L 00383 //0x00AC ATD1DR14H 00384 //0x00AD ATD1DR14L 00385 //0x00AE ATD1DR15H 00386 //0x00AF ATD1DR15L 00387 /* NOT bonded on the 112 pin package!! Left here in case of 144 pin FreeEMS later on. */ 00388 00389 00390 /* IIC1 - Inter Intergrated Circuit interface 1 TODO configure and use */ 00391 //0x00B0 IBAD DVUCP() /* 00392 //0x00B1 IBFD DVUCP() /* 00393 //0x00B2 IBCR DVUCP() /* 00394 //0x00B3 IBSR DVUCP() /* 00395 //0x00B4 IBDR DVUCP() /* 00396 00397 00398 /* SCI2 */ 00399 //0x00B8 SCI2BDH 00400 //0x00B8 SCI2ASR1 00401 //0x00B9 SCI2BDL 00402 //0x00B9 SCI2ACR1 00403 //0x00BA SCI2CR1 00404 //0x00BA SCI2ACR2 00405 //0x00BB SCI2CR2 00406 //0x00BC SCI2SR1 00407 //0x00BD SCI2SR2 00408 //0x00BE SCI2DRH 00409 //0x00BF SCI2DRL 00410 00411 00412 /* SCI3 */ 00413 //0x00C0 SCI3BDH 00414 //0x00C0 SCI3ASR1 00415 //0x00C1 SCI3BDL 00416 //0x00C1 SCI3ACR1 00417 //0x00C2 SCI3CR1 00418 //0x00C2 SCI3ACR2 00419 //0x00C3 SCI3CR2 00420 //0x00C4 SCI3SR1 00421 //0x00C5 SCI3SR2 00422 //0x00C6 SCI3DRH 00423 //0x00C7 SCI3DRL 00424 00425 00426 /* SCI0 debug/comms/datalogging TODO this is our primary serial interface for flash loading, setup serial comms software to communicate with MTX or similar for testing. */ 00427 #define SCI0_BASE 0x00C8 00428 00429 #define SCI0BD DVUSP(SCI0_BASE + 0x0) /* #define SCI0BDH DVUCP(0x00C8), #define SCI0BDL DVUCP(0x00C9) (IR and baud control) */ 00430 #define SCI0CR1 DVUCP(SCI0_BASE + 0x2) /* Control reg 1 */ 00431 00432 #define SCI0ASR1 DVUCP(SCI0_BASE + 0x0) /* Status reg 1a (rx flags) */ 00433 #define SCI0ACR1 DVUCP(SCI0_BASE + 0x1) /* Control reg 1a (rx conf) */ 00434 #define SCI0ACR2 DVUCP(SCI0_BASE + 0x2) /* Control reg 2a (rx conf) */ 00435 00436 #define SCI0CR2 DVUCP(SCI0_BASE + 0x3) /* Control reg 2 */ 00437 #define SCI0SR1 DVUCP(SCI0_BASE + 0x4) /* Status reg 1 (isr flags) */ 00438 #define SCI0SR2 DVUCP(SCI0_BASE + 0x5) /* Status reg 2 (config/control) */ 00439 #define SCI0DRH DVUCP(SCI0_BASE + 0x6) /* Data reg high (9th bit bit 7 receive bit 6 send) */ 00440 #define SCI0DRL DVUCP(SCI0_BASE + 0x7) /* Data reg low (read and write for receive and send respectively)*/ 00441 00442 00443 /* SCI1 debug/comms/datalogging TODO this is our secondary serial interface, setup serial comms software to communicate with MTX or similar for testing. */ 00444 //0x00D0 SCI1BDH 00445 //0x00D1 SCI1BDL 00446 //0x00D2 SCI1CR1 00447 00448 //0x00D0 SCI1ASR1 00449 //0x00D1 SCI1ACR1 00450 //0x00D2 SCI1ACR2 00451 00452 //0x00D3 SCI1CR2 00453 //0x00D4 SCI1SR1 00454 //0x00D5 SCI1SR2 00455 //0x00D6 SCI1DRH 00456 //0x00D7 SCI1DRL 00457 00458 00459 /* SPI0 */ 00460 //0x00D8 SPI0CR1 00461 //0x00D9 SPI0CR2 00462 //0x00DA SPI0BR 00463 //0x00DB SPI0SR 00464 //0x00DD SPI0DR 00465 00466 00467 /* IIC0 */ 00468 //0x00E0 IBAD 00469 //0x00E1 IBFD 00470 //0x00E2 IBCR 00471 //0x00E3 IBSR 00472 //0x00E4 IBDR 00473 00474 00475 /* SPI1 */ 00476 //0x00F0 SPI1CR1 00477 //0x00F1 SPI1CR2 00478 //0x00F2 SPI1BR 00479 //0x00F3 SPI1SR 00480 //0x00F5 SPI1DR 00481 00482 00483 /* SPI2 */ 00484 //0x00F8 SPI2CR1 00485 //0x00F9 SPI2CR2 00486 //0x00FA SPI2BR 00487 //0x00FB SPI2SR 00488 //0x00FD SPI2DR 00489 00490 00491 /* Flash Control Registers */ 00492 #define FCLKDIV DVUCP(0x0100) /* Flash Clock Divider Register R/W */ 00493 #define FSEC DVUCP(0x0101) /* Flash Security Register R */ 00494 #define FCNFG DVUCP(0x0103) /* Flash Configuration Register R/W */ 00495 #define FPROT DVUCP(0x0104) /* Flash Protection Register R/W */ 00496 #define FSTAT DVUCP(0x0105) /* Flash Status Register R/W */ 00497 #define FCMD DVUCP(0x0106) /* Flash Command Register R/W */ 00498 #define FCTL DVUCP(0x0107) /* Flash Control Register R */ 00499 00500 #define FADDR DVUSP(0x0108) /* Flash Low Address Register R (0x0108 FADDRHI, 0x0109 FADDRLO) */ 00501 #define FDATA DVUSP(0x010A) /* Flash High Data Register R (0x010A FDATAHI, 0x010B FDATALO) */ 00502 00503 00504 /* EEPROM Control Registers TODO learn how to use these to write data to the eeprom through serial comms. */ 00505 //0x0110 ECLKDIV 00506 //0x0113 ECNFG 00507 //0x0114 EPROT 00508 //0x0115 ESTAT 00509 //0x0116 ECMD 00510 //0x0118 EADDRHI 00511 //0x0119 EADDRLO 00512 //0x011A EDATAHI 00513 //0x011B EDATALO 00514 00515 00517 #define IVBR DVUCP(0x0121) /* Interrupt vector table base location first byte (second is always 0x00) */ 00518 //0x0126 INT_XGPRIO 00519 //0x0127 INT_CFADDR 00520 //0x0128 INT_CFDATA0 00521 //0x0129 INT_CFDATA1 00522 //0x012A INT_CFDATA2 00523 //0x012B INT_CFDATA3 00524 //0x012C INT_CFDATA4 00525 //0x012D INT_CFDATA5 00526 //0x012E INT_CFDATA6 00527 //0x012F INT_CFDATA7 00528 00529 00530 /* SCI4 */ 00531 //0x0130 SCI4BDH 00532 //0x0130 SCI4ASR1 00533 //0x0131 SCI4BDL 00534 //0x0131 SCI4ACR1 00535 //0x0132 SCI4CR1 00536 //0x0132 SCI4ACR2 00537 //0x0133 SCI4CR2 00538 //0x0134 SCI4SR1 00539 //0x0135 SCI4SR2 00540 //0x0136 SCI4DRH 00541 //0x0137 SCI4DRL 00542 00543 00544 /* SCI5 */ 00545 //0x0138 SCI5BDH 00546 //0x0138 SCI5ASR1 00547 //0x0139 SCI5BDL 00548 //0x0139 SCI5ACR1 00549 //0x013A SCI5CR1 00550 //0x013A SCI5ACR2 00551 //0x013B SCI5CR2 00552 //0x013C SCI5SR1 00553 //0x013D SCI5SR2 00554 //0x013E SCI5DRH 00555 //0x013F SCI5DRL 00556 00557 00558 /* CAN0 don't want this for now, leave it disabled too. CAN0CTL1 bit 7 should be set to zero to disable this. */ 00559 //0x0140 CAN0CTL0 00560 #define CAN0CTL1 DVUCP(0x0141) 00561 //0x0142 CAN0BTR0 00562 //0x0143 CAN0BTR1 00563 //0x0144 CAN0RFLG 00564 //0x0145 CAN0RIER 00565 //0x0146 CAN0TFLG 00566 //0x0147 CAN0TIER 00567 //0x0148 CAN0TARQ 00568 //0x0149 CAN0TAAK 00569 //0x014A CAN0TBSEL 00570 //0x014B CAN0IDAC 00571 //0x014D CAN0MISC 00572 //0x014E CAN0RXERR 00573 //0x014F CAN0TXERR 00574 //0x0150 – 0x0153 : CAN0IDAR0 – CAN0IDAR3 00575 //0x0154 – 0x0157 : CAN0IDMR0 – CAN0IDMR3 00576 //0x0158 – 0x015B : CAN0IDAR4 – CAN0IDAR7 00577 //0x015C – 0x015F : CAN0IDMR4 – CAN0IDMR7 00578 //0x0160 – 0x016F : CAN0RXFG 00579 //0x0170 – 0x017F : CAN0TXFG 00580 00581 00582 //&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& 00583 //this block applies to all can maps!!! 00584 // 00585 //0xXXX0 00586 //Extended ID 00587 //Standard ID 00588 //CANxRIDR0 00589 //0xXXX1 00590 //Extended ID 00591 //Standard ID 00592 //CANxRIDR1 00593 //0xXXX2 00594 //Extended ID 00595 //Standard ID 00596 //CANxRIDR2 00597 //0xXXX3 00598 //Extended ID 00599 //Standard ID 00600 //CANxRIDR3 00601 // 00602 //0xXXX4– 00603 //0xXXXB 00604 //CANxRDSR0– 00605 //CANxRDSR7 00606 //0xXXXC CANRxDLR 00607 //0xXXXD Reserved 00608 //0xXXXE CANxRTSRH 00609 //0xXXXF CANxRTSRL 00610 //0xXX10 00611 //Extended ID 00612 //CANxTIDR0 00613 //Standard ID 00614 // 00615 //0xXX0x 00616 //XX10 00617 //Extended ID 00618 //CANxTIDR1 00619 //Standard ID 00620 //0xXX12 00621 //Extended ID 00622 //CANxTIDR2 00623 //Standard ID 00624 //0xXX13 00625 //Extended ID 00626 //CANxTIDR3 00627 //Standard ID 00628 // 00629 //0xXX14– 00630 //0xXX1B 00631 //CANxTDSR0– 00632 //CANxTDSR7 00633 // 00634 //0xXX1C CANxTDLR 00635 //0xXX1D CANxTTBPR 00636 //0xXX1E CANxTTSRH 00637 //0xXX1F CANxTTSRL 00638 00639 //&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&77 00640 00641 00642 /* CAN1 don't want this for now, leave it disabled too. CAN1CTL1 bit 7 should be set to zero to disable this. */ 00643 //0x0180 CAN1CTL0 00644 #define CAN1CTL1 DVUCP(0x0181) 00645 //0x0182 CAN1BTR0 00646 //0x0183 CAN1BTR1 00647 //0x0184 CAN1RFLG 00648 //0x0185 CAN1RIER 00649 //0x0186 CAN1TFLG 00650 //0x0187 CAN1TIER 00651 //0x0188 CAN1TARQ 00652 //0x0189 CAN1TAAK 00653 //0x018A CAN1TBSEL 00654 //0x018B CAN1IDAC 00655 //0x018D CAN1MISC 00656 //0x018E CAN1RXERR 00657 //0x018F CAN1TXERR 00658 //0x0190 CAN1IDAR0 00659 //0x0191 CAN1IDAR1 00660 //0x0192 CAN1IDAR2 00661 //0x0193 CAN1IDAR3 00662 //0x0194 CAN1IDMR0 00663 //0x0195 CAN1IDMR1 00664 //0x0196 CAN1IDMR2 00665 //0x0197 CAN1IDMR3 00666 //0x0198 CAN1IDAR4 00667 //0x0199 CAN1IDAR5 00668 //0x019A CAN1IDAR6 00669 //0x019B CAN1IDAR7 00670 //0x019C CAN1IDMR4 00671 //0x019D CAN1IDMR5 00672 //0x019E CAN1IDMR6 00673 //0x019F CAN1IDMR7 00674 //0x01A0 – 0x01AF : CAN1RXFG 00675 //0x01B0 – 0x01BF : CAN1TXFG 00676 00677 00678 /* CAN2 CAN2CTL1 bit 7 should be set to zero to disable this. */ 00679 //0x01C0 CAN2CTL0 00680 //0x01C1 CAN2CTL1 00681 //0x01C2 CAN2BTR0 00682 //0x01C3 CAN2BTR1 00683 //0x01C4 CAN2RFLG 00684 //0x01C5 CAN2RIER 00685 //0x01C6 CAN2TFLG 00686 //0x01C7 CAN2TIER 00687 //0x01C8 CAN2TARQ 00688 //0x01C9 CAN2TAAK 00689 //0x01CA CAN2TBSEL 00690 //0x01CB CAN2IDAC 00691 //0x01CD CAN2MISC 00692 //0x01CE CAN2RXERR 00693 //0x01CF CAN2TXERR 00694 //0x01D0 CAN2IDAR0 00695 //0x01D1 CAN2IDAR1 00696 //0x01D2 CAN2IDAR2 00697 //0x01D3 CAN2IDAR3 00698 //0x01D4 CAN2IDMR0 00699 //0x01D5 CAN2IDMR1 00700 //0x01D6 CAN2IDMR2 00701 //0x01D7 CAN2IDMR3 00702 //0x01D8 CAN2IDAR4 00703 //0x01D9 CAN2IDAR5 00704 //0x01DA CAN2IDAR6 00705 //0x01DB CAN2IDAR7 00706 //0x01DC CAN2IDMR4 00707 //0x01DD CAN2IDMR5 00708 //0x01DE CAN2IDMR6 00709 //0x01DF CAN2IDMR7 00710 //0x01E0 – 0x01EF : CAN2RXFG 00711 //0x01F0 – 0x01FF : CAN2TXFG 00712 00713 00714 /* CAN3 CAN3CTL1 bit 7 should be set to zero to disable this. */ 00715 //0x0200 CAN3CTL0 00716 #define CAN3CTL1 DVUCP(0x0201) 00717 //0x0202 CAN3BTR0 00718 //0x0203 CAN3BTR1 00719 //0x0204 CAN3RFLG 00720 //0x0205 CAN3RIER 00721 //0x0206 CAN3TFLG 00722 //0x0207 CAN3TIER 00723 //0x0208 CAN3TARQ 00724 //0x0209 CAN3TAAK 00725 //0x020A CAN3TBSEL 00726 //0x020B CAN3IDAC 00727 //0x020E CAN3RXERR 00728 //0x020F CAN3TXERR 00729 //0x0210 CAN3IDAR0 00730 //0x0211 CAN3IDAR1 00731 //0x0212 CAN3IDAR2 00732 //0x0213 CAN3IDAR3 00733 //0x0214 CAN3IDMR0 00734 //0x0215 CAN3IDMR1 00735 //0x0216 CAN3IDMR2 00736 //0x0217 CAN3IDMR3 00737 //0x0218 CAN3IDAR4 00738 //0x0219 CAN3IDAR5 00739 //0x021A CAN3IDAR6 00740 //0x021B CAN3IDAR7 00741 //0x021C CAN3IDMR4 00742 //0x021D CAN3IDMR5 00743 //0x021E CAN3IDMR6 00744 //0x021F CAN3IDMR7 00745 //0x0220 – 0x022F : CAN3RXFG 00746 //0x0230 – 0x023F : CAN3TXFG 00747 00748 00749 /* CAN4 CAN4CTL1 bit 7 should be set to zero to disable this. */ 00750 //0x0280 CAN4CTL0 00751 #define CAN4CTL1 DVUCP(0x0281) 00752 //0x0282 CAN4BTR0 00753 //0x0283 CAN4BTR1 00754 //0x0284 CAN4RFLG 00755 //0x0285 CAN4RIER 00756 //0x0286 CAN4TFLG 00757 //0x0287 CAN4TIER 00758 //0x0288 CAN4TARQ 00759 //0x0289 CAN4TAAK 00760 //0x028A CAN4TBSEL 00761 //0x028B CAN4IDAC 00762 //0x028D CAN4MISC 00763 //0x028E CAN4RXERR 00764 //0x028F CAN4TXERR 00765 //0x0290 CAN4IDAR0 00766 //0x0291 CAN4IDAR1 00767 //0x0292 CAN4IDAR2 00768 //0x0293 CAN4IDAR3 00769 //0x0294 CAN4IDMR0 00770 //0x0295 CAN4IDMR1 00771 //0x0296 CAN4IDMR2 00772 //0x0297 CAN4IDMR3 00773 //0x0298 CAN4IDAR4 00774 //0x0299 CAN4IDAR5 00775 //0x029A CAN4IDAR6 00776 //0x029B CAN4IDAR7 00777 //0x029C CAN4IDMR4 00778 //0x029D CAN4IDMR5 00779 //0x029E CAN4IDMR6 00780 //0x029F CAN4IDMR7 00781 //0x02A0 – 0x02AF : CAN4RXFG 00782 //0x02B0 – 0x02BF : CAN4TXFG 00783 00784 00785 /* ATD0 TODO configure this as ATD inputs and try them out to control rate of flashing of leds etc, or even, which LED's are flashing etc */ 00786 #define ATD0CTL0 DVUCP(0x02C0) /* 0 - 2 define which ADC channel to wrap on when doing multiple channels */ 00787 #define ATD0CTL1 DVUCP(0x02C1) /* External trigger select when enabled in other control register */ 00788 #define ATD0CTL2 DVUCP(0x02C2) /* bit 7 turns the ADC block on. */ 00789 #define ATD0CTL3 DVUCP(0x02C3) /* bit 6 means conversion length is 8, bit 2 controls how the registers are used, bits 0 - 1 define freeze mode behaviour */ 00790 #define ATD0CTL4 DVUCP(0x02C4) /* bit 7 should be zero meaning 10bit ADC, bits 6,5 are the sample period, and 4,3,2,1,0 are the sample frequency clock scaler */ 00791 #define ATD0CTL5 DVUCP(0x02C5) /* bit 7 sets right justify, bit 5 sets scan mode, bit 4 sets multiplex mode */ 00792 //0x02C6 ATD0STAT0 00793 //0x02CB ATD0STAT1 00794 #define ATD0DIEN DVUCP(0x02CD) /* Digital input enable */ 00795 //0x02CF ATD0PTAD0 digital use only 00796 #define ATD0_BASE 0x02D0 /* Maybe use this with a loop to sample them in a compact way. */ 00797 #define ATD0DR0 DVUSP(ATD0_BASE + 0x0) /* 16 bit (0x02D0 ATD0DR0H, 0x02D1 ATD0DR0L) */ /* IAT/MAT on my JimStim setup */ 00798 #define ATD0DR1 DVUSP(ATD0_BASE + 0x2) /* 16 bit (0x02D2 ATD0DR1H, 0x02D3 ATD0DR1L) */ /* CHT/CLT on my JimStim setup */ 00799 #define ATD0DR2 DVUSP(ATD0_BASE + 0x4) /* 16 bit (0x02D4 ATD0DR2H, 0x02D5 ATD0DR2L) */ /* TPS/TPS on my JimStim setup */ 00800 #define ATD0DR3 DVUSP(ATD0_BASE + 0x6) /* 16 bit (0x02D6 ATD0DR3H, 0x02D7 ATD0DR3L) */ /* EGO/O2 on my JimStim setup */ 00801 #define ATD0DR4 DVUSP(ATD0_BASE + 0x8) /* 16 bit (0x02D8 ATD0DR4H, 0x02D9 ATD0DR4L) */ /* BRV left of 3 one end of my h1 board */ 00802 #define ATD0DR5 DVUSP(ATD0_BASE + 0xA) /* 16 bit (0x02DA ATD0DR5H, 0x02DB ATD0DR5L) */ /* MAP mid of 3 one end of my h1 board */ 00803 #define ATD0DR6 DVUSP(ATD0_BASE + 0xC) /* 16 bit (0x02DC ATD0DR6H, 0x02DD ATD0DR6L) */ /* AAP right of 3 one end of my h1 board */ 00804 #define ATD0DR7 DVUSP(ATD0_BASE + 0xE) /* 16 bit (0x02DE ATD0DR7H, 0x02DF ATD0DR7L) */ /* SpareADC/SPARE on my JimStim setup */ 00805 00806 00807 /* VREG unit, Low Voltage Interrupt and Autonomous Periodical Interrupt */ 00808 #define VREGCTRL DVUCP(0x02F1) /* VReg Control Register */ 00809 #define VREGAPICL DVUCP(0x02F2) /* Autonomous Periodical Interrupt Control Register */ 00810 #define VREGAPITR DVUCP(0x02F3) /* Autonomous Periodical Interrupt Trimming Register */ 00811 #define VREGAPIR DVUSP(0x02F4) /* Autonomous Periodical Interrupt Rate High and Low Registers (VREGAPIRH DVUCP(0x02F4), VREGAPIRL DVUCP(0x02F5)) */ 00812 00813 00814 #define PWME DVUCP(0x0300) /* PWM enable register */ 00815 #define PWMPOL DVUCP(0x0301) /* PWM polarity register */ 00816 #define PWMCLK DVUCP(0x0302) /* PWM clock choice register */ 00817 #define PWMPRCLK DVUCP(0x0303) /* PWM Clock prescalers (bits 0,1,2 and bits 4,5,6 control 4 pins each) */ 00818 #define PWMCAE DVUCP(0x0304) /* PWM Center Align Enable Register */ 00819 #define PWMCTL DVUCP(0x0305) /* PWM Concatenate, stop, wait, freeze register */ 00820 #define PWMSCLA DVUCP(0x0308) /* PWM Scale A register */ 00821 #define PWMSCLB DVUCP(0x0309) /* PWM Scale B register */ 00822 #define PWMCNT0 DVUCP(0x030C) /* PWM 8 bit counter */ 00823 #define PWMCNT1 DVUCP(0x030D) /* */ 00824 #define PWMCNT2 DVUCP(0x030E) /* */ 00825 #define PWMCNT3 DVUCP(0x030F) /* */ 00826 #define PWMCNT4 DVUCP(0x0310) /* */ 00827 #define PWMCNT5 DVUCP(0x0311) /* */ 00828 #define PWMCNT6 DVUCP(0x0312) /* */ 00829 #define PWMCNT7 DVUCP(0x0313) /* PWM 8 bit counter */ 00830 #define PWMPER0 DVUCP(0x0314) /* PWM period value */ /* Ign LED 6 on my JimStim */ 00831 #define PWMPER1 DVUCP(0x0315) /* */ /* Ign LED 4 on my JimStim */ 00832 #define PWMPER2 DVUCP(0x0316) /* */ /* Ign LED 2 on my JimStim */ 00833 #define PWMPER3 DVUCP(0x0317) /* */ /* Ign LED 1 on my JimStim */ 00834 #define PWMPER4 DVUCP(0x0318) /* */ /* Ign LED 3 on my JimStim */ 00835 #define PWMPER5 DVUCP(0x0319) /* */ /* Ign LED 5 on my JimStim */ 00836 #define PWMPER6 DVUCP(0x031A) /* */ /* NC yet */ 00837 #define PWMPER7 DVUCP(0x031B) /* PWM period value */ /* NC yet */ 00838 #define PWMDTY0 DVUCP(0x031C) /* PWM duty cycle value */ 00839 #define PWMDTY1 DVUCP(0x031D) /* */ 00840 #define PWMDTY2 DVUCP(0x031E) /* */ 00841 #define PWMDTY3 DVUCP(0x031F) /* */ 00842 #define PWMDTY4 DVUCP(0x0320) /* */ 00843 #define PWMDTY5 DVUCP(0x0321) /* */ 00844 #define PWMDTY6 DVUCP(0x0322) /* */ 00845 #define PWMDTY7 DVUCP(0x0323) /* PWM duty cycle value */ 00846 #define PWMSDN DVUCP(0x0324) /* PWM shutdown behaviour register */ 00847 00848 00849 /* Periodic Interupt Timer with down counter */ 00850 #define PITCFLMT DVUCP(0x0340) /* PIT Control and Force Load Micro Timer Register, high bit enables, low 2 bits force load micro timers */ 00851 #define PITFLT DVUCP(0x0341) /* PIT Force Load Timer Register, low 4 bits force load timers */ 00852 #define PITCE DVUCP(0x0342) /* PIT Channel Enable Register, low 4 bits let the channel count */ 00853 #define PITMUX DVUCP(0x0343) /* PIT Multiplex Register, low 4 bits set which micro time base is used */ 00854 #define PITINTE DVUCP(0x0344) /* PIT Interrupt Enable Register, low four bits control the ISRs */ 00855 #define PITTF DVUCP(0x0345) /* PIT Time-Out Flag Register, low 4 bits set when each counter reaches 0 */ 00856 #define PITMTLD0 DVUCP(0x0346) /* PIT Micro Timer Load Register 0, time to start counting from when reaching zero */ 00857 #define PITMTLD1 DVUCP(0x0347) /* PIT Micro Timer Load Register 1, time to start counting from when reaching zero */ 00858 #define PITLD0 DVUSP(0x0348) /* PIT Load Register 0, time to start counting from when reaching zero (0x0348 PITLD0 (hi), 0x0349 PITLD0 (lo)) */ 00859 #define PITLD1 DVUSP(0x034C) /* PIT Load Register 1, time to start counting from when reaching zero (0x034C PITLD1 (hi), 0x034D PITLD1 (lo)) */ 00860 #define PITLD2 DVUSP(0x0350) /* PIT Load Register 2, time to start counting from when reaching zero (0x0350 PITLD2 (hi), 0x0351 PITLD2 (lo)) */ 00861 #define PITLD3 DVUSP(0x0354) /* PIT Load Register 3, time to start counting from when reaching zero (0x0354 PITLD3 (hi), 0x0355 PITLD3 (lo)) */ 00862 #define PITCNT0 DVUSP(0x034A) /* PIT Count Register 0, current value of down counter (0x034A PITCNT0 (hi), 0x034B PITCNT0 (lo)) */ 00863 #define PITCNT1 DVUSP(0x034E) /* PIT Count Register 1, current value of down counter (0x034E PITCNT1 (hi), 0x034F PITCNT1 (lo)) */ 00864 #define PITCNT2 DVUSP(0x0352) /* PIT Count Register 2, current value of down counter (0x0352 PITCNT2 (hi), 0x0353 PITCNT2 (lo)) */ 00865 #define PITCNT3 DVUSP(0x0356) /* PIT Count Register 3, current value of down counter (0x0356 PITCNT3 (hi), 0x0357 PITCNT3 (lo)) */ 00866 00867 00868 // TODO XGATE Set up stuff 00869 #define XGMCTL DVUSP(0x0380) /* TODO: 7th bit of this should be set to 0 for now to turn the XGATE off */ 00870 #define XGMCTLHI DVUCP(0x0380) 00871 #define XGMCTLLO DVUCP(0x0381) /* TODO: or 7th bit of this should be set to 0 for now to turn the XGATE off */ 00872 //0x0382 XGCHID 00873 //0x0384 XGVBR 00874 //0x0385 XGVBR 00875 //0x0386 XGVBR 00876 //0x0387 XGVBR 00877 //0x0388 XGIF 00878 //0x0389 XGIF 00879 //0x038A XGIF 00880 //0x023B XGIF /* TODO WRONG value 0x023B stated in the manual as being both xgate and can3!!!!! should be 0x038B i believe!!!!! */ 00881 //0x023C XGIF /* TODO WRONG value 0x023C stated in the manual as being both xgate and can3!!!!! should be 0x038C i believe!!!!! */ 00882 //0x038D XGIF 00883 //0x038E XGIF 00884 //0x038F XGIF 00885 //0x0390 XGIF 00886 //0x0391 XGIF 00887 //0x0392 XGIF 00888 //0x0393 XGIF 00889 //0x0394 XGIF 00890 //0x0395 XGIF 00891 //0x0396 XGIF 00892 //0x0397 XGIF 00893 //0x0398 XGSWT (hi) 00894 //0x0399 XGSWT (lo) 00895 //0x039A XGSEM (hi) 00896 //0x039B XGSEM (lo) 00897 //0x039D XGCCR 00898 //0x039E XGPC (hi) 00899 //0x039F XGPC (lo) 00900 //0x03A2 XGR1 (hi) 00901 //0x03A3 XGR1 (lo) 00902 //0x03A4 XGR2 (hi) 00903 //0x03A5 XGR2 (lo) 00904 //0x03A6 XGR3 (hi) 00905 //0x03A7 XGR3 (lo) 00906 //0x03A8 XGR4 (hi) 00907 //0x03A9 XGR4 (lo) 00908 //0x03AA XGR5 (hi) 00909 //0x03AB XGR5(lo) 00910 //0x03AC XGR6 (hi) 00911 //0x03AD XGR6 (lo) 00912 //0x03AE XGR7 (hi) 00913 //0x03AF XGR7 (lo) 00914 00915 00917 //0x0020 DBGC1 DVUCP() /* 00918 //0x0021 DBGSR DVUCP() /* 00919 //0x0022 DBGTCR DVUCP() /* 00920 //0x0023 DBGC2 DVUCP() /* 00921 //0x0024 DBGTBH DVUCP() /* 00922 //0x0025 DBGTBL DVUCP() /* 00923 //0x0026 DBGCNT DVUCP() /* 00924 //0x0027 DBGSCRX DVUCP() /* 00925 //COMPA 0x0028 DVUCP() /* 00926 //COMPC 0x0028 DVUCP() /* 00927 //DBGXCTL 0x0028 DVUCP() /* 00928 //COMPB 0x0028 DVUCP() /* 00929 //COMPD 0x0028 DVUCP() /* 00930 //0x0029 DBGXAH DVUCP() /* 00931 //0x002A DBGXAM DVUCP() /* 00932 //0x002B DBGXAL DVUCP() /* 00933 //0x002C DBGXDH DVUCP() /* 00934 //0x002D DBGXDL DVUCP() /* 00935 //0x002E DBGXDHM DVUCP() /* 00936 //0x002F DBGXDLM DVUCP() /* 00937 00938 00939 /* All reserved registers/blocks are listed here for reference */ 00940 00941 /* 0x003E CTCTL COP test register */ 00942 /* 0x006D TIMTST Timer test register */ 00943 /* 0x0102 FTSTMOD Flash test register */ 00944 /* 0x02C8 ATD0TEST0 ADC test register */ 00945 /* 0x02C9 ATD0TEST1 ADC test register */ 00946 /* 0x02F0 VREGHTCL VReg test register */ 00947 /* 0x0306 PWMTST PWM test register */ 00948 /* 0x0307 PWMPRSC PWM test register 2 */ 00949 /* 0x030A PWMSCNTA PWM test register 3 */ 00950 /* 0x030B PWMSCNTB PWM test register 4 */ 00951 00952 00953 /* 0x001D Reserved */ 00954 /* 0x001F Reserved */ 00955 /* 0x0012 Reserved */ 00956 /* 0x0014 - 0x0015 : Reserved */ 00957 /* 0x0018 - 0x0019 : Reserved */ 00958 /* 0x0031 Reserved */ 00959 /* 0x006C Reserved */ 00960 /* 0x00B5 - 0x00B7 : Reserved */ 00961 /* 0x0087 Reserved */ 00962 /* 0x00DC Reserved */ 00963 /* 0x00DE - 0x00DF : Reserved */ 00964 /* 0x00E5 - 0x00EF : Reserved */ 00965 /* 0x00F4 Reserved */ 00966 /* 0x00F6 Reserved */ 00967 /* 0x00F7 Reserved */ 00968 /* 0x00FC Reserved */ 00969 /* 0x00FE - 0x00FF : Reserved */ 00970 /* 0x010C - 0x010F : Reserved */ 00971 /* 0x0111 Reserved */ 00972 /* 0x0112 Reserved */ 00973 /* 0x0117 Reserved */ 00974 /* 0x0120 Reserved */ 00975 /* 0x0122 - 0x0125 : Reserved */ 00976 /* 0x014C Reserved */ 00977 /* 0x018C Reserved */ 00978 /* 0x01CC Reserved */ 00979 /* 0x020C - 0x020D : Reserved */ 00980 /* 0x0246 - 0x0247 : Reserved */ 00981 /* 0x024F Reserved */ 00982 /* 0x0270 Reserved */ 00983 /* 0x0272 Reserved */ 00984 /* 0x0274 Reserved */ 00985 /* 0x0276 Reserved */ 00986 /* 0x028C Reserved */ 00987 /* 0x02C7 Reserved */ 00988 /* 0x02CA Reserved */ 00989 /* 0x02CC Reserved */ 00990 /* 0x02CE Reserved */ 00991 /* 0x02E0 – 0x02EF : Reserved */ 00992 /* 0x02F6 – 0x02FF : Reserved */ 00993 /* 0x0325 – 0x033F : Reserved */ 00994 /* 0x0358 – 0x037F : Reserved */ 00995 /* 0x0383 Reserved */ 00996 /* 0x039C Reserved */ 00997 /* 0x03A0 Reserved */ 00998 /* 0x03A1 Reserved */ 00999 /* 0x03B0 – 0x07FF : Reserved */ 01000 01001 01002 /* Clear any accidental use of Reserved from typing mistakes. */ 01003 #ifdef Reserved 01004 #error "We have accidentally defined reserved as Reserved in here, find it and fix it." 01005 #endif 01006 01007 01008 #else 01009 /* let us know if we are being untidy with headers */ 01010 #warning "Header file 9S12XDP512_H seen before, sort it out!" 01011 /* end of the wrapper ifdef from the very top */ 01012 #endif