00001 /* FreeEMS - the open source engine management system 00002 00003 Copyright 2008 Fred Cooke 00004 00005 This file is part of the FreeEMS project. 00006 00007 FreeEMS software is free software: you can redistribute it and/or modify 00008 it under the terms of the GNU General Public License as published by 00009 the Free Software Foundation, either version 3 of the License, or 00010 (at your option) any later version. 00011 00012 FreeEMS software is distributed in the hope that it will be useful, 00013 but WITHOUT ANY WARRANTY; without even the implied warranty of 00014 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00015 GNU General Public License for more details. 00016 00017 You should have received a copy of the GNU General Public License 00018 along with any FreeEMS software. If not, see http://www.gnu.org/licenses/ 00019 00020 We ask that if you make any changes to this file you email them upstream to 00021 us at admin(at)diyefi(dot)org or, even better, fork the code on github.com! 00022 00023 Thank you for choosing FreeEMS to run your engine! */ 00024 00025 00039 #include "inc/freeEMS.h" 00040 #include "inc/interrupts.h" 00041 00042 00043 /* Correctly placed in memory due to compiler/linker directives in memory.x and the linker script. */ 00044 /* This is the FULL table of length 0xFF starting at 0xFF00 and ending at 0xFFFF, redirected with */ 00045 /* jumps to the offset location by the serial monitor starting at 0xF700 and ending at 0xF800 */ 00046 /* http://m68hc11.serveftp.org/wiki/index.php/FAQ:Interrupts */ 00047 const interruptTable _vectors[] VECTORS = { 00048 /* 0xFF00 to 0xFF0F */ 00049 /* The first row are NOT actually interrupts at all, just a wasted 16 bytes for tidiness */ 00050 /* UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, */ 00051 /* Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved */ 00052 /* */ 00053 00054 /* 0xFF10 to 0xFF1F */ 00055 UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, 00056 /* Spurious Reserved Reserved Reserved Reserved Reserved Reserved Reserved */ 00057 /* */ 00058 00059 /* 0xFF20 to 0xFF2F */ 00060 UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, 00061 /* Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved */ 00062 /* */ 00063 00064 /* 0xFF30 to 0xFF3F */ 00065 UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, 00066 /* Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved */ 00067 /* */ 00068 00069 /* 0xFF40 to 0xFF4F */ 00070 UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, 00071 /* Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved */ 00072 /* */ 00073 00074 /* 0xFF50 to 0xFF5F */ 00075 UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, 00076 /* Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved */ 00077 /* */ 00078 00079 /* 0xFF60 to 0xFF6F */ 00080 UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, 00081 /* RAM violation XGATEsoft error XGATE 7 XGATE 6 XGATE 5 XGATE 4 XGATE 3 XGATE 2 */ 00082 /* */ 00083 00084 /* 0xFF70 to 0xFF7F */ 00085 UISR, UISR, StagedOffISR, StagedOnISR, IgnitionFireISR,IgnitionDwellISR,UISR, UISR,//VRegAPIISR, 00086 /* XGATE 1 XGATE 0 PIT 3 PIT 2 PIT 1 PIT 0 Reserved API */ 00087 /* Fire Coil Dwell Coil */ 00088 00089 /* 0xFF80 to 0xFF8F */ 00090 LowVoltageISR, UISR, UISR, UISR, UISR, UISR, UISR, PortPISR, 00091 /* Low Voltage IIC1 SCI5 SCI4 SCI3 SCI2 PWM ESDown Port P */ 00092 /* */ 00093 00094 /* 0xFF90 to 0xFF9F */ 00095 UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, 00096 /* CAN4 Tx CAN4 Rx CAN4 Errors CAN4 Wakeup CAN3 Tx CAN3 Rx CAN3 Errors CAN3 Wakeup */ 00097 /* */ 00098 00099 /* 0xFFA0 to 0xFFAF */ 00100 UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, 00101 /* CAN2 Tx CAN2 Rx CAN2 Errors CAN2 Wakeup CAN1 Tx CAN1 Rx CAN1 Errors CAN1 Wakeup */ 00102 /* */ 00103 00104 /* 0xFFB0 to 0xFFBF */ 00105 UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, 00106 /* CAN0 Tx CAN0 Rx CAN0 Errors CAN0 Wakeup FLASH EEPROM SPI2 SPI1 */ 00107 /* */ 00108 00109 /* 0xFFC0 to 0xFFCF */ 00110 UISR, UISR, UISR, UISR, UISR, ModDownCtrISR, PortHISR, PortJISR, 00111 /* IIC0 Reserved CRG self clock CRG PLL lock PAB Overflow ModDwnCtrUF Port H Port J */ 00112 /* */ 00113 00114 /* 0xFFD0 to 0xFFDF */ 00115 UISR, UISR, UISR, SCI0ISR, UISR, UISR, UISR, TimerOverflow, 00116 /* ATD1 ATD0? SCI1 SCI0 SPI0 PAIE PAA OF ECT OF */ 00117 /* Serial 0 */ 00118 00119 /* 0xFFE0 to 0xFFEF */ 00120 Injector6ISR, Injector5ISR, Injector4ISR, Injector3ISR, Injector2ISR, Injector1ISR, SecondaryRPMISR,PrimaryRPMISR, 00121 /* ECT7 ECT6 ECT5 ECT4 ECT3 ECT2 ECT1 ECT0 */ 00122 /* Injector 6 Injector 5 Injector 4 Injector 3 Injector 2 Injector 1 Secondary RPM Primary RPM */ 00123 00124 /* 0xFFF0 to 0xFFFF */ 00125 RTIISR, IRQISR, XIRQISR, UISR, UISR, UISR, UISR, _start 00126 /* RTI IRQ XIRQ SWI UnimpInstruct COP Reset ClockReset SystemReset */ 00127 /* Entry point */ 00128 };