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Defines | |
#define | DVUCP(address) (*((volatile unsigned char*)(address))) |
#define | DVUSP(address) (*((volatile unsigned short*)(address))) |
#define | AVUCP(address) ((volatile unsigned char*)(address)) |
#define | AVUSP(address) ((volatile unsigned short*)(address)) |
#define | PORTS_BA DVUSP(0x0001) |
#define | PORTA DVUCP(0x0000) |
#define | PORTB DVUCP(0x0001) |
#define | PORTE DVUCP(0x0008) |
#define | PORTK DVUCP(0x0032) |
#define | DDRA DVUCP(0x0002) |
#define | DDRB DVUCP(0x0003) |
#define | DDRE DVUCP(0x0009) |
#define | DDRK DVUCP(0x0033) |
#define | DDRC DVUCP(0x0006) |
#define | DDRD DVUCP(0x0007) |
#define | PUCR DVUCP(0x000C) |
#define | RDRIV DVUCP(0x000D) |
#define | ECLKCTL DVUCP(0x001C) |
#define | IRQCR DVUCP(0x001E) |
#define | PTT DVUCP(0x0240) |
#define | PORTT DVUCP(0x0240) |
#define | PTIT DVUCP(0x0241) |
#define | DDRT DVUCP(0x0242) |
#define | RDRT DVUCP(0x0243) |
#define | PERT DVUCP(0x0244) |
#define | PPST DVUCP(0x0245) |
#define | PTS DVUCP(0x0248) |
#define | PORTS DVUCP(0x0248) |
#define | PTIS DVUCP(0x0249) |
#define | DDRS DVUCP(0x024A) |
#define | RDRS DVUCP(0x024B) |
#define | PERS DVUCP(0x024C) |
#define | PPSS DVUCP(0x024D) |
#define | WOMS DVUCP(0x024E) |
#define | PTM DVUCP(0x0250) |
#define | PORTM DVUCP(0x0250) |
#define | PTIM DVUCP(0x0251) |
#define | DDRM DVUCP(0x0252) |
#define | RDRM DVUCP(0x0253) |
#define | PERM DVUCP(0x0254) |
#define | PPSM DVUCP(0x0255) |
#define | WOMM DVUCP(0x0256) |
#define | MODRR DVUCP(0x0257) |
#define | PTP DVUCP(0x0258) |
#define | PORTP DVUCP(0x0258) |
#define | PTIP DVUCP(0x0259) |
#define | DDRP DVUCP(0x025A) |
#define | RDRP DVUCP(0x025B) |
#define | PERP DVUCP(0x025C) |
#define | PPSP DVUCP(0x025D) |
#define | PIEP DVUCP(0x025E) |
#define | PIFP DVUCP(0x025F) |
#define | PTH DVUCP(0x0260) |
#define | PORTH DVUCP(0x0260) |
#define | PTIH DVUCP(0x0261) |
#define | DDRH DVUCP(0x0262) |
#define | RDRH DVUCP(0x0263) |
#define | PERH DVUCP(0x0264) |
#define | PPSH DVUCP(0x0265) |
#define | PIEH DVUCP(0x0266) |
#define | PIFH DVUCP(0x0267) |
#define | PTJ DVUCP(0x0268) |
#define | PORTJ DVUCP(0x0268) |
#define | PTIJ DVUCP(0x0269) |
#define | DDRJ DVUCP(0x026A) |
#define | RDRJ DVUCP(0x026B) |
#define | PERJ DVUCP(0x026C) |
#define | PPSJ DVUCP(0x026D) |
#define | PIEJ DVUCP(0x026E) |
#define | PIFJ DVUCP(0x026F) |
#define | ATD0PER1 DVUCP(0x0277) |
#define | RPAGE DVUCP(0x0016) |
#define | PPAGE DVUCP(0x0030) |
#define | SYNR DVUCP(0x0034) |
#define | REFDV DVUCP(0x0035) |
#define | CRGFLG DVUCP(0x0037) |
#define | CRGINT DVUCP(0x0038) |
#define | CLKSEL DVUCP(0x0039) |
#define | PLLCTL DVUCP(0x003A) |
#define | RTICTL DVUCP(0x003B) |
#define | COPCTL DVUCP(0x003C) |
#define | ARMCOP DVUCP(0x003F) |
#define | TCNT DVUSP(0x0044) |
#define | TIOS DVUCP(0x0040) |
#define | TIE DVUCP(0x004C) |
#define | TSCR1 DVUCP(0x0046) |
#define | TSCR2 DVUCP(0x004D) |
#define | TFLG DVUCP(0x004E) |
#define | TFLGOF DVUCP(0x004F) |
#define | PTPSR DVUCP(0x006E) |
#define | TTOV DVUCP(0x0047) |
#define | CFORC DVUCP(0x0041) |
#define | OC7M DVUCP(0x0042) |
#define | OC7D DVUCP(0x0043) |
#define | TCTL1 DVUCP(0x0048) |
#define | TCTL2 DVUCP(0x0049) |
#define | TCTL1_ADDR AVUCP(0x0048) |
#define | TCTL2_ADDR AVUCP(0x0049) |
#define | DLYCT DVUCP(0x0069) |
#define | ICSYS DVUCP(0x006B) |
#define | ICOVW DVUCP(0x006A) |
#define | TCTL3 DVUCP(0x004A) |
#define | TCTL4 DVUCP(0x004B) |
#define | TC0H DVUSP(0x0078) |
#define | TC1H DVUSP(0x007A) |
#define | TC2H DVUSP(0x007C) |
#define | TC3H DVUSP(0x007E) |
#define | TC0 DVUSP(0x0050) |
#define | TC1 DVUSP(0x0052) |
#define | TC2 DVUSP(0x0054) |
#define | TC3 DVUSP(0x0056) |
#define | TC4 DVUSP(0x0058) |
#define | TC5 DVUSP(0x005A) |
#define | TC6 DVUSP(0x005C) |
#define | TC7 DVUSP(0x005E) |
#define | TC2_ADDR AVUSP(0x0054) |
#define | TC3_ADDR AVUSP(0x0056) |
#define | TC4_ADDR AVUSP(0x0058) |
#define | TC5_ADDR AVUSP(0x005A) |
#define | TC6_ADDR AVUSP(0x005C) |
#define | TC7_ADDR AVUSP(0x005E) |
#define | MCCTL DVUCP(0x0066) |
#define | MCFLG DVUCP(0x0067) |
#define | MCCNT DVUSP(0x0076) |
#define | PTMCPSR DVUCP(0x006F) |
#define | ATD1CTL0 DVUCP(0x0080) |
#define | ATD1CTL1 DVUCP(0x0081) |
#define | ATD1CTL2 DVUCP(0x0082) |
#define | ATD1CTL3 DVUCP(0x0083) |
#define | ATD1CTL4 DVUCP(0x0084) |
#define | ATD1CTL5 DVUCP(0x0085) |
#define | ATD1DIEN0 DVUCP(0x008C) |
#define | ATD1DIEN1 DVUCP(0x008D) |
#define | ATD1_BASE 0x0090 |
#define | ATD1DR0 DVUSP(ATD1_BASE + 0x0) /* 16 bit (0x0090 ATD1DR0H, 0x0091 ATD1DR0L) */ |
#define | ATD1DR1 DVUSP(ATD1_BASE + 0x2) /* 16 bit (0x0092 ATD1DR1H, 0x0093 ATD1DR1L) */ |
#define | ATD1DR2 DVUSP(ATD1_BASE + 0x4) /* 16 bit (0x0094 ATD1DR2H, 0x0095 ATD1DR2L) */ |
#define | ATD1DR3 DVUSP(ATD1_BASE + 0x6) /* 16 bit (0x0096 ATD1DR3H, 0x0097 ATD1DR3L) */ |
#define | ATD1DR4 DVUSP(ATD1_BASE + 0x8) /* 16 bit (0x0098 ATD1DR4H, 0x0099 ATD1DR4L) */ |
#define | ATD1DR5 DVUSP(ATD1_BASE + 0xA) /* 16 bit (0x009A ATD1DR5H, 0x009B ATD1DR5L) */ |
#define | ATD1DR6 DVUSP(ATD1_BASE + 0xC) /* 16 bit (0x009C ATD1DR6H, 0x009D ATD1DR6L) */ |
#define | ATD1DR7 DVUSP(ATD1_BASE + 0xE) /* 16 bit (0x009E ATD1DR7H, 0x009F ATD1DR7L) */ |
#define | SCI0_BASE 0x00C8 |
#define | SCI0BD DVUSP(SCI0_BASE + 0x0) |
#define | SCI0CR1 DVUCP(SCI0_BASE + 0x2) |
#define | SCI0ASR1 DVUCP(SCI0_BASE + 0x0) |
#define | SCI0ACR1 DVUCP(SCI0_BASE + 0x1) |
#define | SCI0ACR2 DVUCP(SCI0_BASE + 0x2) |
#define | SCI0CR2 DVUCP(SCI0_BASE + 0x3) |
#define | SCI0SR1 DVUCP(SCI0_BASE + 0x4) |
#define | SCI0SR2 DVUCP(SCI0_BASE + 0x5) |
#define | SCI0DRH DVUCP(SCI0_BASE + 0x6) |
#define | SCI0DRL DVUCP(SCI0_BASE + 0x7) |
#define | FCLKDIV DVUCP(0x0100) |
#define | FSEC DVUCP(0x0101) |
#define | FCNFG DVUCP(0x0103) |
#define | FPROT DVUCP(0x0104) |
#define | FSTAT DVUCP(0x0105) |
#define | FCMD DVUCP(0x0106) |
#define | FCTL DVUCP(0x0107) |
#define | FADDR DVUSP(0x0108) |
#define | FDATA DVUSP(0x010A) |
#define | IVBR DVUCP(0x0121) |
#define | CAN0CTL1 DVUCP(0x0141) |
#define | CAN1CTL1 DVUCP(0x0181) |
#define | CAN3CTL1 DVUCP(0x0201) |
#define | CAN4CTL1 DVUCP(0x0281) |
#define | ATD0CTL0 DVUCP(0x02C0) |
#define | ATD0CTL1 DVUCP(0x02C1) |
#define | ATD0CTL2 DVUCP(0x02C2) |
#define | ATD0CTL3 DVUCP(0x02C3) |
#define | ATD0CTL4 DVUCP(0x02C4) |
#define | ATD0CTL5 DVUCP(0x02C5) |
#define | ATD0DIEN DVUCP(0x02CD) |
#define | ATD0_BASE 0x02D0 |
#define | ATD0DR0 DVUSP(ATD0_BASE + 0x0) /* 16 bit (0x02D0 ATD0DR0H, 0x02D1 ATD0DR0L) */ |
#define | ATD0DR1 DVUSP(ATD0_BASE + 0x2) /* 16 bit (0x02D2 ATD0DR1H, 0x02D3 ATD0DR1L) */ |
#define | ATD0DR2 DVUSP(ATD0_BASE + 0x4) /* 16 bit (0x02D4 ATD0DR2H, 0x02D5 ATD0DR2L) */ |
#define | ATD0DR3 DVUSP(ATD0_BASE + 0x6) /* 16 bit (0x02D6 ATD0DR3H, 0x02D7 ATD0DR3L) */ |
#define | ATD0DR4 DVUSP(ATD0_BASE + 0x8) /* 16 bit (0x02D8 ATD0DR4H, 0x02D9 ATD0DR4L) */ |
#define | ATD0DR5 DVUSP(ATD0_BASE + 0xA) /* 16 bit (0x02DA ATD0DR5H, 0x02DB ATD0DR5L) */ |
#define | ATD0DR6 DVUSP(ATD0_BASE + 0xC) /* 16 bit (0x02DC ATD0DR6H, 0x02DD ATD0DR6L) */ |
#define | ATD0DR7 DVUSP(ATD0_BASE + 0xE) /* 16 bit (0x02DE ATD0DR7H, 0x02DF ATD0DR7L) */ |
#define | VREGCTRL DVUCP(0x02F1) |
#define | VREGAPICL DVUCP(0x02F2) |
#define | VREGAPITR DVUCP(0x02F3) |
#define | VREGAPIR DVUSP(0x02F4) |
#define | PWME DVUCP(0x0300) |
#define | PWMPOL DVUCP(0x0301) |
#define | PWMCLK DVUCP(0x0302) |
#define | PWMPRCLK DVUCP(0x0303) |
#define | PWMCAE DVUCP(0x0304) |
#define | PWMCTL DVUCP(0x0305) |
#define | PWMSCLA DVUCP(0x0308) |
#define | PWMSCLB DVUCP(0x0309) |
#define | PWMCNT0 DVUCP(0x030C) |
#define | PWMCNT1 DVUCP(0x030D) |
#define | PWMCNT2 DVUCP(0x030E) |
#define | PWMCNT3 DVUCP(0x030F) |
#define | PWMCNT4 DVUCP(0x0310) |
#define | PWMCNT5 DVUCP(0x0311) |
#define | PWMCNT6 DVUCP(0x0312) |
#define | PWMCNT7 DVUCP(0x0313) |
#define | PWMPER0 DVUCP(0x0314) /* PWM period value */ |
#define | PWMPER1 DVUCP(0x0315) /* */ |
#define | PWMPER2 DVUCP(0x0316) /* */ |
#define | PWMPER3 DVUCP(0x0317) /* */ |
#define | PWMPER4 DVUCP(0x0318) /* */ |
#define | PWMPER5 DVUCP(0x0319) /* */ |
#define | PWMPER6 DVUCP(0x031A) /* */ |
#define | PWMPER7 DVUCP(0x031B) /* PWM period value */ |
#define | PWMDTY0 DVUCP(0x031C) |
#define | PWMDTY1 DVUCP(0x031D) |
#define | PWMDTY2 DVUCP(0x031E) |
#define | PWMDTY3 DVUCP(0x031F) |
#define | PWMDTY4 DVUCP(0x0320) |
#define | PWMDTY5 DVUCP(0x0321) |
#define | PWMDTY6 DVUCP(0x0322) |
#define | PWMDTY7 DVUCP(0x0323) |
#define | PWMSDN DVUCP(0x0324) |
#define | PITCFLMT DVUCP(0x0340) |
#define | PITFLT DVUCP(0x0341) |
#define | PITCE DVUCP(0x0342) |
#define | PITMUX DVUCP(0x0343) |
#define | PITINTE DVUCP(0x0344) |
#define | PITTF DVUCP(0x0345) |
#define | PITMTLD0 DVUCP(0x0346) |
#define | PITMTLD1 DVUCP(0x0347) |
#define | PITLD0 DVUSP(0x0348) |
#define | PITLD1 DVUSP(0x034C) |
#define | PITLD2 DVUSP(0x0350) |
#define | PITLD3 DVUSP(0x0354) |
#define | PITCNT0 DVUSP(0x034A) |
#define | PITCNT1 DVUSP(0x034E) |
#define | PITCNT2 DVUSP(0x0352) |
#define | PITCNT3 DVUSP(0x0356) |
#define | XGMCTL DVUSP(0x0380) |
#define | XGMCTLHI DVUCP(0x0380) |
#define | XGMCTLLO DVUCP(0x0381) |
#define ARMCOP DVUCP(0x003F) |
#define ATD0_BASE 0x02D0 |
#define ATD0CTL0 DVUCP(0x02C0) |
Definition at line 769 of file 9S12XDP512.h.
#define ATD0CTL1 DVUCP(0x02C1) |
Definition at line 770 of file 9S12XDP512.h.
#define ATD0CTL2 DVUCP(0x02C2) |
#define ATD0CTL3 DVUCP(0x02C3) |
#define ATD0CTL4 DVUCP(0x02C4) |
Definition at line 773 of file 9S12XDP512.h.
#define ATD0CTL5 DVUCP(0x02C5) |
#define ATD0DIEN DVUCP(0x02CD) |
#define ATD0DR0 DVUSP(ATD0_BASE + 0x0) /* 16 bit (0x02D0 ATD0DR0H, 0x02D1 ATD0DR0L) */ |
#define ATD0DR1 DVUSP(ATD0_BASE + 0x2) /* 16 bit (0x02D2 ATD0DR1H, 0x02D3 ATD0DR1L) */ |
#define ATD0DR2 DVUSP(ATD0_BASE + 0x4) /* 16 bit (0x02D4 ATD0DR2H, 0x02D5 ATD0DR2L) */ |
#define ATD0DR3 DVUSP(ATD0_BASE + 0x6) /* 16 bit (0x02D6 ATD0DR3H, 0x02D7 ATD0DR3L) */ |
#define ATD0DR4 DVUSP(ATD0_BASE + 0x8) /* 16 bit (0x02D8 ATD0DR4H, 0x02D9 ATD0DR4L) */ |
#define ATD0DR5 DVUSP(ATD0_BASE + 0xA) /* 16 bit (0x02DA ATD0DR5H, 0x02DB ATD0DR5L) */ |
#define ATD0DR6 DVUSP(ATD0_BASE + 0xC) /* 16 bit (0x02DC ATD0DR6H, 0x02DD ATD0DR6L) */ |
#define ATD0DR7 DVUSP(ATD0_BASE + 0xE) /* 16 bit (0x02DE ATD0DR7H, 0x02DF ATD0DR7L) */ |
#define ATD0PER1 DVUCP(0x0277) |
Definition at line 166 of file 9S12XDP512.h.
#define ATD1_BASE 0x0090 |
#define ATD1CTL0 DVUCP(0x0080) |
#define ATD1CTL1 DVUCP(0x0081) |
Definition at line 327 of file 9S12XDP512.h.
#define ATD1CTL2 DVUCP(0x0082) |
#define ATD1CTL3 DVUCP(0x0083) |
#define ATD1CTL4 DVUCP(0x0084) |
Definition at line 330 of file 9S12XDP512.h.
#define ATD1CTL5 DVUCP(0x0085) |
#define ATD1DIEN0 DVUCP(0x008C) |
#define ATD1DIEN1 DVUCP(0x008D) |
#define ATD1DR0 DVUSP(ATD1_BASE + 0x0) /* 16 bit (0x0090 ATD1DR0H, 0x0091 ATD1DR0L) */ |
#define ATD1DR1 DVUSP(ATD1_BASE + 0x2) /* 16 bit (0x0092 ATD1DR1H, 0x0093 ATD1DR1L) */ |
#define ATD1DR2 DVUSP(ATD1_BASE + 0x4) /* 16 bit (0x0094 ATD1DR2H, 0x0095 ATD1DR2L) */ |
#define ATD1DR3 DVUSP(ATD1_BASE + 0x6) /* 16 bit (0x0096 ATD1DR3H, 0x0097 ATD1DR3L) */ |
#define ATD1DR4 DVUSP(ATD1_BASE + 0x8) /* 16 bit (0x0098 ATD1DR4H, 0x0099 ATD1DR4L) */ |
#define ATD1DR5 DVUSP(ATD1_BASE + 0xA) /* 16 bit (0x009A ATD1DR5H, 0x009B ATD1DR5L) */ |
#define ATD1DR6 DVUSP(ATD1_BASE + 0xC) /* 16 bit (0x009C ATD1DR6H, 0x009D ATD1DR6L) */ |
#define ATD1DR7 DVUSP(ATD1_BASE + 0xE) /* 16 bit (0x009E ATD1DR7H, 0x009F ATD1DR7L) */ |
#define AVUCP | ( | address | ) | ((volatile unsigned char*)(address)) |
Definition at line 44 of file 9S12XDP512.h.
#define AVUSP | ( | address | ) | ((volatile unsigned short*)(address)) |
Definition at line 46 of file 9S12XDP512.h.
#define CAN0CTL1 DVUCP(0x0141) |
Definition at line 543 of file 9S12XDP512.h.
#define CAN1CTL1 DVUCP(0x0181) |
Definition at line 627 of file 9S12XDP512.h.
#define CAN3CTL1 DVUCP(0x0201) |
Definition at line 699 of file 9S12XDP512.h.
#define CAN4CTL1 DVUCP(0x0281) |
Definition at line 734 of file 9S12XDP512.h.
#define CFORC DVUCP(0x0041) |
Definition at line 243 of file 9S12XDP512.h.
#define CLKSEL DVUCP(0x0039) |
Definition at line 218 of file 9S12XDP512.h.
#define COPCTL DVUCP(0x003C) |
#define CRGFLG DVUCP(0x0037) |
#define CRGINT DVUCP(0x0038) |
#define DDRA DVUCP(0x0002) |
#define DDRB DVUCP(0x0003) |
#define DDRC DVUCP(0x0006) |
#define DDRD DVUCP(0x0007) |
#define DDRE DVUCP(0x0009) |
#define DDRH DVUCP(0x0262) |
#define DDRJ DVUCP(0x026A) |
#define DDRK DVUCP(0x0033) |
#define DDRM DVUCP(0x0252) |
#define DDRP DVUCP(0x025A) |
#define DDRS DVUCP(0x024A) |
#define DDRT DVUCP(0x0242) |
#define DLYCT DVUCP(0x0069) |
Definition at line 260 of file 9S12XDP512.h.
#define DVUCP | ( | address | ) | (*((volatile unsigned char*)(address))) |
Definition at line 39 of file 9S12XDP512.h.
#define DVUSP | ( | address | ) | (*((volatile unsigned short*)(address))) |
Definition at line 41 of file 9S12XDP512.h.
#define ECLKCTL DVUCP(0x001C) |
Definition at line 87 of file 9S12XDP512.h.
#define FADDR DVUSP(0x0108) |
Definition at line 483 of file 9S12XDP512.h.
#define FCLKDIV DVUCP(0x0100) |
#define FCMD DVUCP(0x0106) |
#define FCNFG DVUCP(0x0103) |
Definition at line 477 of file 9S12XDP512.h.
#define FCTL DVUCP(0x0107) |
Definition at line 481 of file 9S12XDP512.h.
#define FDATA DVUSP(0x010A) |
Definition at line 484 of file 9S12XDP512.h.
#define FPROT DVUCP(0x0104) |
#define FSEC DVUCP(0x0101) |
Definition at line 476 of file 9S12XDP512.h.
#define FSTAT DVUCP(0x0105) |
Definition at line 479 of file 9S12XDP512.h.
Referenced by eraseSector(), initFlash(), and writeWord().
#define ICOVW DVUCP(0x006A) |
Definition at line 262 of file 9S12XDP512.h.
#define ICSYS DVUCP(0x006B) |
Definition at line 261 of file 9S12XDP512.h.
#define IRQCR DVUCP(0x001E) |
Definition at line 88 of file 9S12XDP512.h.
#define IVBR DVUCP(0x0121) |
#define MCCNT DVUSP(0x0076) |
#define MCCTL DVUCP(0x0066) |
#define MCFLG DVUCP(0x0067) |
#define MODRR DVUCP(0x0257) |
Definition at line 124 of file 9S12XDP512.h.
#define OC7D DVUCP(0x0043) |
Definition at line 245 of file 9S12XDP512.h.
#define OC7M DVUCP(0x0042) |
Definition at line 244 of file 9S12XDP512.h.
#define PERH DVUCP(0x0264) |
Definition at line 145 of file 9S12XDP512.h.
#define PERJ DVUCP(0x026C) |
Definition at line 157 of file 9S12XDP512.h.
#define PERM DVUCP(0x0254) |
Definition at line 118 of file 9S12XDP512.h.
#define PERP DVUCP(0x025C) |
Definition at line 133 of file 9S12XDP512.h.
#define PERS DVUCP(0x024C) |
Definition at line 107 of file 9S12XDP512.h.
#define PERT DVUCP(0x0244) |
Definition at line 97 of file 9S12XDP512.h.
#define PIEH DVUCP(0x0266) |
#define PIEJ DVUCP(0x026E) |
Definition at line 159 of file 9S12XDP512.h.
#define PIEP DVUCP(0x025E) |
Definition at line 135 of file 9S12XDP512.h.
#define PIFH DVUCP(0x0267) |
#define PIFJ DVUCP(0x026F) |
#define PIFP DVUCP(0x025F) |
#define PITCE DVUCP(0x0342) |
Definition at line 835 of file 9S12XDP512.h.
Referenced by IgnitionDwellISR(), IgnitionFireISR(), and PrimaryRPMISR().
#define PITCFLMT DVUCP(0x0340) |
#define PITCNT0 DVUSP(0x034A) |
#define PITCNT1 DVUSP(0x034E) |
#define PITCNT2 DVUSP(0x0352) |
Definition at line 847 of file 9S12XDP512.h.
#define PITCNT3 DVUSP(0x0356) |
Definition at line 848 of file 9S12XDP512.h.
#define PITFLT DVUCP(0x0341) |
Definition at line 834 of file 9S12XDP512.h.
#define PITINTE DVUCP(0x0344) |
Definition at line 837 of file 9S12XDP512.h.
Referenced by IgnitionDwellISR(), IgnitionFireISR(), PrimaryRPMISR(), StagedOffISR(), and StagedOnISR().
#define PITLD0 DVUSP(0x0348) |
Definition at line 841 of file 9S12XDP512.h.
Referenced by IgnitionDwellISR(), IgnitionFireISR(), and PrimaryRPMISR().
#define PITLD1 DVUSP(0x034C) |
#define PITLD2 DVUSP(0x0350) |
Definition at line 843 of file 9S12XDP512.h.
#define PITLD3 DVUSP(0x0354) |
Definition at line 844 of file 9S12XDP512.h.
#define PITMTLD0 DVUCP(0x0346) |
#define PITMTLD1 DVUCP(0x0347) |
#define PITMUX DVUCP(0x0343) |
Definition at line 836 of file 9S12XDP512.h.
#define PITTF DVUCP(0x0345) |
Definition at line 838 of file 9S12XDP512.h.
Referenced by IgnitionDwellISR(), IgnitionFireISR(), and PrimaryRPMISR().
#define PLLCTL DVUCP(0x003A) |
Definition at line 219 of file 9S12XDP512.h.
#define PORTA DVUCP(0x0000) |
Definition at line 55 of file 9S12XDP512.h.
Referenced by initIO(), ModDownCtrISR(), PortHISR(), and SCI0ISR().
#define PORTB DVUCP(0x0001) |
#define PORTE DVUCP(0x0008) |
#define PORTH DVUCP(0x0260) |
#define PORTJ DVUCP(0x0268) |
Definition at line 153 of file 9S12XDP512.h.
Referenced by initIO(), main(), PrimaryRPMISR(), and SecondaryRPMISR().
#define PORTK DVUCP(0x0032) |
Definition at line 58 of file 9S12XDP512.h.
Referenced by decodePacketAndRespond(), initIO(), and main().
#define PORTM DVUCP(0x0250) |
#define PORTP DVUCP(0x0258) |
#define PORTS DVUCP(0x0248) |
Definition at line 103 of file 9S12XDP512.h.
Referenced by IgnitionDwellISR(), IgnitionFireISR(), and initIO().
#define PORTS_BA DVUSP(0x0001) |
Definition at line 54 of file 9S12XDP512.h.
Referenced by IgnitionDwellISR(), IgnitionFireISR(), and initConfiguration().
#define PORTT DVUCP(0x0240) |
#define PPAGE DVUCP(0x0030) |
Definition at line 190 of file 9S12XDP512.h.
Referenced by decodePacketAndRespond(), eraseSector(), lookupBlockDetails(), and writeSector().
#define PPSH DVUCP(0x0265) |
#define PPSJ DVUCP(0x026D) |
Definition at line 158 of file 9S12XDP512.h.
#define PPSM DVUCP(0x0255) |
Definition at line 119 of file 9S12XDP512.h.
#define PPSP DVUCP(0x025D) |
Definition at line 134 of file 9S12XDP512.h.
#define PPSS DVUCP(0x024D) |
Definition at line 108 of file 9S12XDP512.h.
#define PPST DVUCP(0x0245) |
Definition at line 98 of file 9S12XDP512.h.
#define PTH DVUCP(0x0260) |
Definition at line 140 of file 9S12XDP512.h.
#define PTIH DVUCP(0x0261) |
Definition at line 142 of file 9S12XDP512.h.
#define PTIJ DVUCP(0x0269) |
Definition at line 154 of file 9S12XDP512.h.
#define PTIM DVUCP(0x0251) |
Definition at line 115 of file 9S12XDP512.h.
#define PTIP DVUCP(0x0259) |
Definition at line 130 of file 9S12XDP512.h.
#define PTIS DVUCP(0x0249) |
Definition at line 104 of file 9S12XDP512.h.
#define PTIT DVUCP(0x0241) |
Definition at line 94 of file 9S12XDP512.h.
Referenced by InjectorXISR(), PrimaryRPMISR(), and SecondaryRPMISR().
#define PTJ DVUCP(0x0268) |
Definition at line 152 of file 9S12XDP512.h.
#define PTM DVUCP(0x0250) |
Definition at line 113 of file 9S12XDP512.h.
#define PTMCPSR DVUCP(0x006F) |
#define PTP DVUCP(0x0258) |
Definition at line 128 of file 9S12XDP512.h.
#define PTPSR DVUCP(0x006E) |
#define PTS DVUCP(0x0248) |
Definition at line 102 of file 9S12XDP512.h.
#define PTT DVUCP(0x0240) |
Definition at line 92 of file 9S12XDP512.h.
#define PUCR DVUCP(0x000C) |
Definition at line 78 of file 9S12XDP512.h.
#define PWMCAE DVUCP(0x0304) |
Definition at line 801 of file 9S12XDP512.h.
#define PWMCLK DVUCP(0x0302) |
#define PWMCNT0 DVUCP(0x030C) |
Definition at line 805 of file 9S12XDP512.h.
#define PWMCNT1 DVUCP(0x030D) |
Definition at line 806 of file 9S12XDP512.h.
#define PWMCNT2 DVUCP(0x030E) |
Definition at line 807 of file 9S12XDP512.h.
#define PWMCNT3 DVUCP(0x030F) |
Definition at line 808 of file 9S12XDP512.h.
#define PWMCNT4 DVUCP(0x0310) |
Definition at line 809 of file 9S12XDP512.h.
#define PWMCNT5 DVUCP(0x0311) |
Definition at line 810 of file 9S12XDP512.h.
#define PWMCNT6 DVUCP(0x0312) |
Definition at line 811 of file 9S12XDP512.h.
#define PWMCNT7 DVUCP(0x0313) |
Definition at line 812 of file 9S12XDP512.h.
#define PWMCTL DVUCP(0x0305) |
Definition at line 802 of file 9S12XDP512.h.
#define PWMDTY0 DVUCP(0x031C) |
#define PWMDTY1 DVUCP(0x031D) |
#define PWMDTY2 DVUCP(0x031E) |
#define PWMDTY3 DVUCP(0x031F) |
#define PWMDTY4 DVUCP(0x0320) |
#define PWMDTY5 DVUCP(0x0321) |
#define PWMDTY6 DVUCP(0x0322) |
#define PWMDTY7 DVUCP(0x0323) |
#define PWME DVUCP(0x0300) |
#define PWMPER0 DVUCP(0x0314) /* PWM period value */ |
#define PWMPER1 DVUCP(0x0315) /* */ |
#define PWMPER2 DVUCP(0x0316) /* */ |
#define PWMPER3 DVUCP(0x0317) /* */ |
#define PWMPER4 DVUCP(0x0318) /* */ |
#define PWMPER5 DVUCP(0x0319) /* */ |
#define PWMPER6 DVUCP(0x031A) /* */ |
#define PWMPER7 DVUCP(0x031B) /* PWM period value */ |
#define PWMPOL DVUCP(0x0301) |
Definition at line 798 of file 9S12XDP512.h.
#define PWMPRCLK DVUCP(0x0303) |
#define PWMSCLA DVUCP(0x0308) |
#define PWMSCLB DVUCP(0x0309) |
#define PWMSDN DVUCP(0x0324) |
Definition at line 829 of file 9S12XDP512.h.
#define RDRH DVUCP(0x0263) |
Definition at line 144 of file 9S12XDP512.h.
#define RDRIV DVUCP(0x000D) |
Definition at line 84 of file 9S12XDP512.h.
#define RDRJ DVUCP(0x026B) |
Definition at line 156 of file 9S12XDP512.h.
#define RDRM DVUCP(0x0253) |
Definition at line 117 of file 9S12XDP512.h.
#define RDRP DVUCP(0x025B) |
Definition at line 132 of file 9S12XDP512.h.
#define RDRS DVUCP(0x024B) |
Definition at line 106 of file 9S12XDP512.h.
#define RDRT DVUCP(0x0243) |
Definition at line 96 of file 9S12XDP512.h.
#define REFDV DVUCP(0x0035) |
Definition at line 214 of file 9S12XDP512.h.
#define RPAGE DVUCP(0x0016) |
Definition at line 188 of file 9S12XDP512.h.
Referenced by decodePacketAndRespond(), initPagedRAMFuel(), initPagedRAMTime(), initPagedRAMTune(), lookupPagedMainTableCellValue(), setPagedMainTableCellValue(), setPagedMainTableLoadValue(), setPagedMainTableRPMValue(), setPagedTwoDTableAxisValue(), setPagedTwoDTableCellValue(), setupPagedRAM(), and writeSector().
#define RTICTL DVUCP(0x003B) |
#define SCI0_BASE 0x00C8 |
Definition at line 410 of file 9S12XDP512.h.
#define SCI0ACR1 DVUCP(SCI0_BASE + 0x1) |
Definition at line 416 of file 9S12XDP512.h.
#define SCI0ACR2 DVUCP(SCI0_BASE + 0x2) |
Definition at line 417 of file 9S12XDP512.h.
#define SCI0ASR1 DVUCP(SCI0_BASE + 0x0) |
Definition at line 415 of file 9S12XDP512.h.
#define SCI0BD DVUSP(SCI0_BASE + 0x0) |
#define SCI0CR1 DVUCP(SCI0_BASE + 0x2) |
#define SCI0CR2 DVUCP(SCI0_BASE + 0x3) |
Definition at line 419 of file 9S12XDP512.h.
Referenced by checksumAndSend(), initSCIStuff(), main(), resetReceiveState(), and SCI0ISR().
#define SCI0DRH DVUCP(SCI0_BASE + 0x6) |
Definition at line 422 of file 9S12XDP512.h.
#define SCI0DRL DVUCP(SCI0_BASE + 0x7) |
Definition at line 423 of file 9S12XDP512.h.
Referenced by checksumAndSend(), SCI0ISR(), and sendAndIncrement().
#define SCI0SR1 DVUCP(SCI0_BASE + 0x4) |
#define SCI0SR2 DVUCP(SCI0_BASE + 0x5) |
Definition at line 421 of file 9S12XDP512.h.
#define SYNR DVUCP(0x0034) |
Definition at line 213 of file 9S12XDP512.h.
#define TC0 DVUSP(0x0050) |
#define TC0H DVUSP(0x0078) |
Definition at line 274 of file 9S12XDP512.h.
#define TC1 DVUSP(0x0052) |
#define TC1H DVUSP(0x007A) |
Definition at line 275 of file 9S12XDP512.h.
#define TC2 DVUSP(0x0054) |
Definition at line 282 of file 9S12XDP512.h.
#define TC2_ADDR AVUSP(0x0054) |
#define TC2H DVUSP(0x007C) |
Definition at line 276 of file 9S12XDP512.h.
#define TC3 DVUSP(0x0056) |
Definition at line 283 of file 9S12XDP512.h.
#define TC3_ADDR AVUSP(0x0056) |
#define TC3H DVUSP(0x007E) |
Definition at line 277 of file 9S12XDP512.h.
#define TC4 DVUSP(0x0058) |
Definition at line 284 of file 9S12XDP512.h.
#define TC4_ADDR AVUSP(0x0058) |
#define TC5 DVUSP(0x005A) |
Definition at line 285 of file 9S12XDP512.h.
#define TC5_ADDR AVUSP(0x005A) |
#define TC6 DVUSP(0x005C) |
Definition at line 286 of file 9S12XDP512.h.
#define TC6_ADDR AVUSP(0x005C) |
#define TC7 DVUSP(0x005E) |
Definition at line 287 of file 9S12XDP512.h.
#define TC7_ADDR AVUSP(0x005E) |
#define TCNT DVUSP(0x0044) |
Definition at line 230 of file 9S12XDP512.h.
Referenced by InjectorXISR(), main(), PrimaryRPMISR(), RTIISR(), SCI0ISR(), and SecondaryRPMISR().
#define TCTL1 DVUCP(0x0048) |
#define TCTL1_ADDR AVUCP(0x0048) |
#define TCTL2 DVUCP(0x0049) |
#define TCTL2_ADDR AVUCP(0x0049) |
#define TCTL3 DVUCP(0x004A) |
#define TCTL4 DVUCP(0x004B) |
#define TFLG DVUCP(0x004E) |
Definition at line 237 of file 9S12XDP512.h.
Referenced by initECTTimer(), InjectorXISR(), PrimaryRPMISR(), and SecondaryRPMISR().
#define TFLGOF DVUCP(0x004F) |
Definition at line 238 of file 9S12XDP512.h.
Referenced by initECTTimer(), InjectorXISR(), PrimaryRPMISR(), SecondaryRPMISR(), and TimerOverflow().
#define TIE DVUCP(0x004C) |
Definition at line 234 of file 9S12XDP512.h.
Referenced by initECTTimer(), InjectorXISR(), and PrimaryRPMISR().
#define TIOS DVUCP(0x0040) |
#define TSCR1 DVUCP(0x0046) |
#define TSCR2 DVUCP(0x004D) |
#define TTOV DVUCP(0x0047) |
Definition at line 242 of file 9S12XDP512.h.
#define VREGAPICL DVUCP(0x02F2) |
Definition at line 792 of file 9S12XDP512.h.
#define VREGAPIR DVUSP(0x02F4) |
Definition at line 794 of file 9S12XDP512.h.
#define VREGAPITR DVUCP(0x02F3) |
Definition at line 793 of file 9S12XDP512.h.
#define VREGCTRL DVUCP(0x02F1) |
#define WOMM DVUCP(0x0256) |
Definition at line 120 of file 9S12XDP512.h.
#define WOMS DVUCP(0x024E) |
Definition at line 109 of file 9S12XDP512.h.
#define XGMCTL DVUSP(0x0380) |
Definition at line 852 of file 9S12XDP512.h.
#define XGMCTLHI DVUCP(0x0380) |
Definition at line 853 of file 9S12XDP512.h.
#define XGMCTLLO DVUCP(0x0381) |
Definition at line 854 of file 9S12XDP512.h.